DDRIII+HPCII глюки или руки? Опции

[billidean]

Всех с праздником, мужики.
Уже неделю сижу с проблемой::
есть код (примерный):

Код

...
...
    write_data_in    : in std_logic_vector(63 downto 0);
...
    read_data_out    : out std_logic_vector(63 downto 0);
    rdata_valid_out    : out std_logic := '0';
...
...

    local_size <= "010";

process( phy_clk )
    variable var_local_address : std_logic_vector(23 downto 0) := ( others => '0' );
    variable counter_write : integer := 0;
    variable counter_read_req  : integer := 0;
    variable counter_read_data : integer := 0;
begin

    case( step ) is
    ---
    when step_pre            =>
                    if( start_write == '1' ) then
                        counter_write := 100;
                        step := step_write_first;
                    end if;
                    if( start_read == '1' ) then
                        counter_read_req  := 100;
                        counter_read_data := 100;
                        step := step_read;
                    end if;
                    local_burstbegin    <= '0';
                    local_write_req    <= '0';
                    local_read_req    <= '0';
                    local_address    <= ( others => '0' ); --начинаю с 0-го адреса
                    var_local_address    <= ( others => '0' ); --начинаю с 0-го адреса
    ---
    when step_write_first    =>
                    if( counter_write = 0 ) then
                        local_address     <= ( others => '0' );
                        local_write_req   <= '0';
                        local_burstbegin  <= '0';
                        step := step_pre;
                    else
                        if( local_ready = '1' ) then
                            local_address     <= var_local_address;
                            local_write_req   <= '1';
                            local_burstbegin  <= '1';
                            local_write_data(63 downto 0)  <= write_data_in(63 downto 0);
                            step := step_write_second;
                        end if;
                    end if;
    ---
    when step_write_second    =>
                    local_burstbegin  <= '0';
                    counter_write       := counter_write - 1;
                    var_local_address <= (инкремент var_local_address)
                    step := step_write_first;
    ---
    when step_read            =>
                    if( counter_read_req = 0 ) then
                        local_address      <= ( others => '0' );
                        local_read_req    <= '0';
                        local_burstbegin  <= '0';
                        step := step_pre;
                    else
                        if( local_ready = '1' ) then
                            local_address     <= var_local_address;
                            local_read_req    <= '1';
                            local_burstbegin  <= '1';
                            var_local_address <= (инкремент var_local_address)
                            counter_read_req := counter_read_req - 1;
                        end if;
                    end if;
                    if( counter_read_data = 0 ) then
                        rdata_valid_out <= '0';
                        step := step_pre;
                    else
                        if( local_rdata_valid = '1' ) then
                            rdata_valid_out <= '1';
                            read_data_out(63 downto 0) <= local_rdata(63 downto 0);
                            counter_read_data := counter_read_data - 1;
                        else
                            rdata_valid_out <= '0';
                        end if;
                    end if;
    end case;

end process;

На железе (Stratix IV) получаю данные read_data_out правильные процентов на 99, а 1% битые.
Почему так???

Не совсем вник в то, когда менять адрес относительно сигнала local_burstbegin, по фронту или по спаду бурста.