UltraScale ASIC-class Programmable Architecture от Xilinx Опции

[maugli]

• 20nm
• Massive data flow optimized for wide buses that support multi-terabit throughput
• Multi-region ASIC-like clocking, power management, and next generation security
• Highly optimized critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing
• Step function in inter-die bandwidth for 2^nd generation 3D IC systems integration
• Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface
• Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance