- 20nm
- Massive data flow optimized for wide buses that support multi-terabit throughput
- Multi-region ASIC-like clocking, power management, and next generation security
- Highly optimized critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing
- Step function in inter-die bandwidth for 2nd generation 3D IC systems integration
- Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface
- Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance
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Форум разработчиков электроники ELECTRONIX.ru > Программируемая логика ПЛИС (FPGA,CPLD, PLD) > Работаем с ПЛИС, области применения, выбор
Цитата(maugli @ Jul 10 2013, 00:09) 
- 20nm
- Massive data flow optimized for wide buses that support multi-terabit throughput
- Multi-region ASIC-like clocking, power management, and next generation security
- Highly optimized critical paths and built-in high-speed memory, cascading to remove bottlenecks in DSP and packet processing
- Step function in inter-die bandwidth for 2nd generation 3D IC systems integration
- Massive I/O and memory bandwidth with dramatic latency reduction and 3D IC wide memory-optimized interface
- Elimination of routing congestion and co-optimization with Vivado tools for >90% device utilization without degradation in performance
это реклама или что Вы этим хотели сказать?
PS На сайте хилых уже это видел...
2 maugli
когда щупать можно ?
когда щупать можно ?
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