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Тогда сложнее очень бы посоветовал почитать даташит например вот что написано на длл для виртекс-е: "Input Clock Changes
Changing the period of the input clock beyond the maximum
drift amount requires a manual reset of the CLKDLL. Failure
to reset the DLL produces an unreliable lock signal and output
clock.
It is possible to stop the input clock with little impact to the
DLL. Stopping the clock should be limited to less than
100 µs to keep device cooling to a minimum. The clock
should be stopped during a Low phase, and when restored
the full High period should be seen. During this time,
LOCKED stays High and remains High when the clock is
restored.
When the clock is stopped, one to four more clocks are still
observed as the delay line is flushed. When the clock is
restarted, the output clocks are not observed for one to four
clocks as the delay line is filled. The most common case is
two or three clocks.
In a similar manner, a phase shift of the input clock is also
possible. The phase shift propagates to the output one to
four clocks after the original shift, with no disruption to the
CLKDLL control."
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Подача синхротактов на ПЛИС., Если отключить подачу тактов?
May 23 2005, 11:10
