extern "C" void UART_IRQ_Handler()
{
    LedBlink();
}

volatile uint16_t index;
const uint8_t TestStr[]="0123456789\n";
void main()
{
    InitUART();
    LPC_UART->IER=1<<LPC_UART_IER_THRE;
    NVIC_EnableIRQ(UART_IRQn);
    for (index=0; TestStr[index]; index++)
        LPC_UART->THR=TestStr[index];
    while (1);
}

#define TX_FIFO_SIZE 128
struct TUartTxBuffer {
    volatile uint8_t TxBuffer[TX_FIFO_SIZE];
    volatile uint8_t TxNext;
    volatile uint8_t TxFirst;
    volatile int8_t IntEnabled;
    INLINE_FUNCTION    void Send_Handler() {
        uint32_t iir=LPC_UART->IIR;
        uint8_t tx_next=TxNext, tx_first=TxFirst;
        uint_fast8_t fifo_free_size=16;
        while (tx_next!=tx_first && fifo_free_size) {
            LPC_UART->THR=TxBuffer[tx_first++];
            fifo_free_size--;
            if (tx_first==TX_FIFO_SIZE)
                tx_first=0;
        }
        TxFirst=tx_first;
        if (tx_next==tx_first) {
            LPC_UART->IER=0;
            IntEnabled=0;
        }
    }
    void SendBuffer(const uint8_t *data_for_send, uint8_t byte_count);
};
void TUartTxBuffer::SendBuffer(const uint8_t *data_for_send, uint8_t byte_count) {
    uint8_t tx_next=TxNext;
    for (uint_fast8_t i=0; i<byte_count; i++) {
        TxBuffer[tx_next++]=*data_for_send++;
        if (tx_next>=TX_FIFO_SIZE)
            tx_next=0;
    }
    NVIC_DisableIRQ(UART_IRQn);
    TxNext=tx_next;
    if (IntEnabled==0) {
        uint8_t tx_first=TxFirst;
        LPC_UART->THR=TxBuffer[tx_first++];
        if (tx_first==TX_FIFO_SIZE)
            tx_first=0;
        TxFirst=tx_first;
        LPC_UART->IER=1<<LPC_UART_IER_THRE;
        IntEnabled=1;
    }
    NVIC_EnableIRQ(UART_IRQn);
}
TUartTxBuffer UartTxBuffer;
extern "C" void UART_IRQ_Handler()
{
    UartTxBuffer.Send_Handler();
}

OS_INTERRUPT void uart0ISRHandler()
{
    OS::TISRW ISRW;
    uint32_t iir;

    // While there are pending interrupts
    while( !( ( iir = U0IIR ) & 1 ) )
    {
        switch( ( iir >> 1 ) & 7UL )
        {
        case 2:
            // Receive data available
        case 6:
            // CTI
            rx_isr_byte = U0RBR;
            getPacketEF.signal_isr();
            break;

        case 1:
            // THRE Interrupt
            U0THR = *pOutBuffer++;
            if( pOutBuffer == pEndBuffer )
            {
                // Disable THRE Interrupt
                U0IER &= ~THRE_IE;
                pOutBuffer = outBuffer;
                sendFinishedEF.signal_isr();
            }
            break;
        }
    }

    IRQ_DONE();
}

template<uint_fast8_t rx_size, uint_fast8_t tx_size>
void buffered_uart<rx_size, tx_size>::send(uint8_t byte)
{
    TCritSect cs;
    if(!Tx_buffer.get_count())
    {
        uint_fast8_t FIFO_counter_cache = Tx_fifo_counter;
        if(pUART->LSR & UART_LSR_THRE)    // FIFO empty
            FIFO_counter_cache = 0;

        if(FIFO_counter_cache < 16)
        {
            if(pUART->LSR & UART_LSR_THRE)    // FIFO empty
                FIFO_counter_cache = 0;
            pUART->THR = byte;
            Tx_fifo_counter = FIFO_counter_cache + 1;
            return;
        }
    }
    Tx_buffer.push(byte);
    pUART->IER = UART_IER_RBRINT_EN | UART_IER_THREINT_EN;
}

template<uint_fast8_t rx_size, uint_fast8_t tx_size>
void buffered_uart<rx_size, tx_size>::send(char const* string)
{
    TCritSect cs;
    if(!Tx_buffer.get_count())
    {
        uint_fast32_t FIFO_counter_cache = Tx_fifo_counter;
        if(pUART->LSR & UART_LSR_THRE)    // FIFO empty
            FIFO_counter_cache = 0;
        while(FIFO_counter_cache < 16)
        {
            char c = *string++;
            if(!c)
            {
                Tx_fifo_counter = FIFO_counter_cache;
                return;
            }
            if(pUART->LSR & UART_LSR_THRE)    // FIFO empty
                FIFO_counter_cache = 0;

            pUART->THR = c;
            ++FIFO_counter_cache;
        }
        Tx_fifo_counter = FIFO_counter_cache;
    }

    while(char c = *string++)
    {
        Tx_buffer.push(c);
        pUART->IER = UART_IER_RBRINT_EN | UART_IER_THREINT_EN;
    }
}

template<uint_fast8_t rx_size, uint_fast8_t tx_size>
void buffered_uart<rx_size, tx_size>::handler()
{
    uint_fast32_t Tmp = pUART->IIR;
    while (!(Tmp & UART_IIR_INTSTAT_PEND))
    {
        switch((Tmp & UART_IIR_INTID_MASK) >> 1)
        {
        case UART_IIR_INTID_CTI >> 1:
        case UART_IIR_INTID_RDA >> 1:
            while (pUART->LSR & UART_LSR_RDR)       // while bytes in RX FIFO
            {
                uint8_t Data = pUART->RBR;          // read anyway
                if(Rx_buffer.get_free_size())
                    Rx_buffer.push(Data);           // if overflow - sorry
            }
            break;

        case UART_IIR_INTID_THRE >> 1:              // Tx interrupt
            {
                uint_fast16_t Queued_bytes = Tx_buffer.get_count();
                if(Queued_bytes)
                {
                    if(Queued_bytes > 16)
                        Queued_bytes = 16;
                    do
                    {
                        uint8_t Data;
                        Tx_buffer.pop(Data, 1);
                        pUART->THR = Data;
                    }
                    while(--Queued_bytes);
                    Tx_fifo_counter = Queued_bytes;
                }
                else
                {
                    Tx_fifo_counter = 0;
                    pUART->IER = UART_IER_RBRINT_EN;

                }
            }
            break;

        case UART1_IIR_INTID_MODEM >> 1:
        case UART_IIR_INTID_RLS >> 1:             // Rx error (OE, PE, FE)
        default:
                break;
        }
        Tmp = pUART->IIR;
    }
}

void sendBuffer()
{
    pEndBuffer = pOutBuffer;
    pOutBuffer = outBuffer;

    U0THR = *pOutBuffer++;
    sendFinishedEF.clear();
    // Enable THRE interrupt
    U0IER |= THRE_IE;
    sendFinishedEF.wait();

    getPacketEF.clear();
}

bool wakePHYGet( uint8_t* byte )
{
    if( !getPacketEF.wait( FWAKE_ONE_BYTE_RX_TIMEOUT ) )
        return false;

    *byte = rx_isr_byte;
    return true;
}

        case 1:
            // THRE Interrupt
            while( pOutBuffer < pEndBuffer )
                U0THR = *pOutBuffer++;

            // Disable THRE Interrupt
            U0IER &= ~THRE_IE;
            pOutBuffer = outBuffer;
            sendFinishedEF.signal_isr();
            break;

InitUart();
    __disable_irq();
    LPC_UART->IER=0;
    LPC_UART->THR='1';
    Delay1s();
    LPC_UART->IER=(1<<LPC_UART_IER_THRE_EN);
    NVIC_EnableIRQ(UART_IRQn);
    __enable_irq();

if (((LPC_UART->LSR & (1<<THRE))&&((LPC_UART->LSR & (1<<THRE))) {
  // тут файфо пустое и никаких прерыаний по пустому файфо не будет
  // посылаю первый байт нового сообщения
}
else {
  // а тут инициировать нельзя: обработчик сам увидет, что надо посылать новое сообщение
}