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-- преобразование из диф. пары в сигнал (clk)
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Ext_clk_IBUFGDS : IBUFGDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16"
IOSTANDARD => "LVDS_33"
)
port map (
O => Ext_clk, -- Clock buffer output
I => clk_in_diff_p, -- Diff_p clock buffer input (connect directly to top-level port)
IB => clk_in_diff_n -- Diff_n clock buffer input (connect directly to top-level port)
);
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gen1 : signgen -- генератор гармонического сигнала
PORT MAP (
clk => ext_clk,
cosine => cosine,
sine => sine
);
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mult_re : signmult -- умножитель
PORT MAP (
clk => ext_clk,
a => cosine,
b => buff_temp(14),
p => to_fir_re
);