TI_CC_SPISetup();                         // Initialize SPI port
    TI_CC_PowerupResetCCxxxx();               // Reset CCxxxx
    writeRFSettings();                        // Write RF settings to config reg
    TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE

      TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
   TI_CC_SPIStrobe(TI_CCxxx0_SFRX);
   TI_CC_SPIStrobe(TI_CCxxx0_SFTX);
   TI_CC_SPIStrobe(TI_CCxxx0_SRX);      

   RX_OFF;  // ЭТО вход RX_EN


while (1)
       {      
          
     RF_TX_Buffer[0]=22;
                          
         for (i=1;i<64;i++) { RF_TX_Buffer[i]=i+F;}          //
        
        
         TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, RF_TX_Buffer, 23); //  

         TX_ON;
         TI_CC_SPIStrobe(TI_CCxxx0_STX);         //
        

        while (!(CCxx00_GD0));
        while (CCxx00_GD0);

       TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
        TI_CC_SPIStrobe(TI_CCxxx0_SFTX);              //
        TX_OFF;
      
                
                
       }

TX_OFF;
     RX_ON;
    
TI_CC_SPISetup();
TI_CC_PowerupResetCCxxxx();


    writeRFSettings();                        // Write RF settings to config reg
    TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
    

TI_CC_SPIStrobe(TI_CCxxx0_SIDLE);
   TI_CC_SPIStrobe(TI_CCxxx0_SFRX);
   TI_CC_SPIStrobe(TI_CCxxx0_SFTX);
   TI_CC_SPIStrobe(TI_CCxxx0_SRX);

void writeRFSettings(void)
{

TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,0x0c); // ??? 0x06
TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,0x00); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,0x10); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,0xA7); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,0x62);  //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,0x2d);  //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,0x3B); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,0x13); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,0x22); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,0xF8);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,0x00); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,0x62); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,0x56);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,0x10); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM2,0x07);  //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1,0x30); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0,0x18); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,0x16); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,0x6C);  //OK
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2,0x03);  //OK
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1,0x40); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0,0x91); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,0xEA);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,0x2A); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,0x00); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,0x1F); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,0x59); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,0x88);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,0x31);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,0x09);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,0x0E);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,0x06);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1,0x0C);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0,0x0D);//OK
TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,0x01); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,0x00); //OK
TI_CC_SPIWriteReg(TI_CCxxx0_FIFOTHR,0x07); //OK
}