int main(void)
{
    cli();

    OSC_XOSCCTRL = OSC_FRQRANGE_12TO16_gc |
                   OSC_XOSCSEL_EXTCLK_gc;
    OSC_CTRL = OSC_XOSCEN_bm;
    while(!(OSC_STATUS & OSC_XOSCRDY_bm)) {; }

    CPU_CCP = CCP_IOREG_gc;
    CLK_CTRL = CLK_SCLKSEL_XOSC_gc;
    OSC_CTRL &= 0xFE;

    EVSYS_CH0MUX = EVSYS_CHMUX_PRESCALER_1_gc;      // ClkPER div by 2^0 is event source
    PORTCFG_CLKEVOUT = PORTCFG_EVOUT_PE7_gc;        // Event Channel 7 Output on Port E pin 7
                                                    //  PORTCFG_CLKOUT_PE7_gc = (0x03<<0)

    PORTA_DIR = 0b00000000;
    PORTB_DIR = 0b11111111;
    PORTC_DIR = 0b00000000;
    PORTD_DIR = 0b00000000;
    PORTE_DIR = 0b10000000;             // PE7 must be configured as output for the event to be available on the pin
    PORTF_DIR = 0b00000000;
    PORTH_DIR = 0b00000000;
    PORTJ_DIR = 0b00011000;
    PORTK_DIR = 0b00000000;
    PORTQ_DIR = 0b0000;

    while (1)
    {
        asm ("nop");
    }
}

#include <avr/io.h>
#include <stdint.h>
#include <stdlib.h>
#include <avr/interrupt.h>


int main(void)
{
    cli();

    PORTA_DIR = 0b00000000;
    PORTB_DIR = 0b11111111;
    PORTC_DIR = 0b00000000;
    PORTD_DIR = 0b00000000;
    PORTE_DIR = 0b10000000;                              // PE7 must be configured as output for the event to be available on the pin
    PORTF_DIR = 0b00000000;
    PORTH_DIR = 0b00000000;
    PORTJ_DIR = 0b00011000;
    PORTK_DIR = 0b00000000;
    PORTQ_DIR = 0b0000;

    while (1)
    {
        PORTB_OUT = 0x55;
        asm ("nop");
        PORTB_OUT = 0xAA;
    }
}

// Clock Source Select
  CCP = CCP_IOREG_gc;                       // 0xD8 - protected IO register
  CLK.PSCTRL = 0x00;                        // Select prescaler A division ratio "1", no division

  OSC.XOSCCTRL = 0x4B;                      // FRQRANGE[1:0] set to (2 MHz - 9 MHz), XOSCSEL[3:0] set to (0.4 - 16 MHz XTAL, 16K CLK)
  OSC.CTRL = OSC_XOSCEN_bm;                 // 0x08 - external oscillator enable
  OSC.XOSCFAIL = OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm;  // 0x03 - failure detection interrupt flag and set XOSCFDEN: failure detection enable
  while( !(OSC.STATUS & OSC_XOSCRDY_bm));   // 0x08 - wait until external clock source is stable and then select it for PLL clock input

  CCP = CCP_IOREG_gc;                       // 0xD8 - protected IO register
  CLK.CTRL = CLK_SCLKSEL_XOSC_gc;           // 0x03 - XOSC - external oscillator or clock

CLK_init:
    ldi    RTMPA,OSC_XOSCSEL_EXTCLK_gc
    sts    (OSC_XOSCCTRL),RTMPA

    lds    RTMPA,(OSC_CTRL)
    ori    RTMPA,OSC_XOSCEN_bm
    sts    (OSC_CTRL),RTMPA

    lds    RTMPA,(OSC_STATUS)
    sbrs    RTMPA,OSC_XOSCRDY_bp
    rjmp    PC-3

    ldi    RTMPA,CCP_IOREG_gc
    sts    (CPU_CCP),RTMPA
    ldi    RTMPA,CLK_SCLKSEL_XOSC_gc
    sts    (CLK_CTRL),RTMPA

    ret

int main (void)
{
    cli ();

    PORTA_DIR = 0b00000000;
    PORTB_DIR = 0b11111111;                                 // PORTB to OUTPUT
    PORTC_DIR = 0b00000000;
    PORTD_DIR = 0b00000000;
    PORTE_DIR = 0b10000000;                                 // PE7 must be configured as output for the event to be available on the pin
    PORTF_DIR = 0b00000000;
    PORTH_DIR = 0b00000000;
    PORTJ_DIR = 0b00011000;
    PORTK_DIR = 0b00000000;
    PORTQ_DIR = 0b0000;

    CPU_CCP = CCP_IOREG_gc;                                 // Enable change of the protected I/O registers
    CLK_PSCTRL = CLK_PSADIV_1_gc | CLK_PSBCDIV_1_1_gc;      // Select prescaler A, B & C division ratio "1", no division

    OSC_XOSCCTRL = OSC_FRQRANGE_04TO2_gc |
                   OSC_XOSCSEL_EXTCLK_gc;                   // External Clock with 6 CLK Start-up Time
    OSC_CTRL |= OSC_XOSCEN_bm;                              // External Oscillator Enable
    while (!(OSC_STATUS & OSC_XOSCRDY_bm)) {; }             // Waiting for external clock source stable

    CPU_CCP = CCP_IOREG_gc;                                 // Enable change of the protected I/O registers
    CLK_CTRL = CLK_SCLKSEL_XOSC_gc;                         // Switch to external oscillator or clock
    OSC_CTRL &= ~OSC_RC2MEN_bm;                             // Disable RC2M

    PORTCFG_CLKEVOUT = PORTCFG_CLKOUT_PE7_gc;               // ClkPER Output on Port E pin 7

    while (1)
    {
        PORTB_OUTTGL = 0xFF;                                // PORTB test meander
    }
}

    PORTC_DIR = 0b00000001;

    TCC0_CTRLA    = TC_CLKSEL_DIV1_gc;                      // DIV1, Prescaler: Clk
    TCC0_CTRLB    = TC0_CCAEN_bm | TC_WGMODE_SS_gc;         // CCAEN = 1, Single-slope PWM operation
    TCC0_CTRLD    = TC_EVACT_OFF_gc | TC_EVSEL_OFF_gc;      // No Event Action, No Event Source
    TCC0_CTRLE    = 0;                                      // NORMAL, TCC0 is set to normal mode (timer/counter type 0)
    TCC0_PER      = 0xC34E;                                 // TOP = 0xFFFF
    TCC0_CCA      = 0x61A7;                                 // Non-buffering method
    TCC0_INTCTRLA = TC_ERRINTLVL_OFF_gc |
                    TC_OVFINTLVL_OFF_gc;                    // Error Interrupt Disabled, Overflow Interrupt Disabled
    TCC0_INTCTRLB = TC_CCDINTLVL_OFF_gc |                   // Compare or Capture D...A Interrupts Disabled
                    TC_CCCINTLVL_OFF_gc |
                    TC_CCBINTLVL_OFF_gc |
                    TC_CCAINTLVL_OFF_gc;