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Вопрос, почему переменной counter_wr, в некоторые разряды проникла клоковая частота, в данном случае counter_wr[5] ? Как с этим бороться?
Прилагаю и кусок кода, чтобы было понятно, что такое counter_wr.
Код
signal counter_rd : integer range low_level to 33554431 :=low_level;
signal counter_wr : integer range low_level to 33554431 :=low_level;
signal read_or_write : integer range low_level to 33554431 :=low_level;
signal rg_read_or_write : integer range low_level to 33554431 :=low_level;
signal count : std_logic; -- сигнал, разрешающий считать счетчику counter_wr
signal rg_write_on_FTDI : std_logic;
begin
--------------------------------------------------------------
---======= смена текущего состояния с.машины
--------------------------------------------------------------
process(clk, clk_en, sclr, next_state, N_valid, cur_state, rg_valid, count)
begin
if rising_edge(clk) then
if sclr = '1' then
----------
cur_state <= st_check_counter;
---------------
rg_valid <= '0';
---------------
rg_read_from_m <= '1';
rg_write_to_m <= '1';
---------------
rg_address <= (others => '0');
---------------
counter_wr <= low_level;
counter_rd <= low_level;
---------------
rg_read_or_write <= low_level;
rg_write_on_FTDI <= '0';
----------
elsif clk_en = '1' then
----------
cur_state <= next_state;
---------------
rg_valid <= N_valid;
---------------
rg_address <= N_address;
---------------
if N_write_to_m = '0' then
counter_wr <= counter_wr+1;
else counter_wr <= counter_wr;
end if;
---------------
if count = '1' then
counter_rd <= counter_rd+1;
rg_write_on_FTDI <= '1';
else counter_rd <= counter_rd;
rg_write_on_FTDI <= rg_write_on_FTDI;
end if;
---------------
rg_read_from_m <= N_read_from_m;
rg_write_to_m <= N_write_to_m;
---------------
rg_read_or_write <= read_or_write;
----------
else
----------
cur_state <= cur_state;
---------------
rg_valid <= rg_valid;
---------------
rg_read_from_m <= rg_read_from_m;
rg_write_to_m <= rg_write_to_m;
---------------
counter_wr <= counter_wr;
counter_rd <= counter_rd;
---------------
rg_address <= rg_address;
---------------
rg_read_or_write <= rg_read_or_write;
rg_write_on_FTDI <= rg_write_on_FTDI;
----------
end if;
end if;
end process;
--============================================================
--============================================================
signal counter_wr : integer range low_level to 33554431 :=low_level;
signal read_or_write : integer range low_level to 33554431 :=low_level;
signal rg_read_or_write : integer range low_level to 33554431 :=low_level;
signal count : std_logic; -- сигнал, разрешающий считать счетчику counter_wr
signal rg_write_on_FTDI : std_logic;
begin
--------------------------------------------------------------
---======= смена текущего состояния с.машины
--------------------------------------------------------------
process(clk, clk_en, sclr, next_state, N_valid, cur_state, rg_valid, count)
begin
if rising_edge(clk) then
if sclr = '1' then
----------
cur_state <= st_check_counter;
---------------
rg_valid <= '0';
---------------
rg_read_from_m <= '1';
rg_write_to_m <= '1';
---------------
rg_address <= (others => '0');
---------------
counter_wr <= low_level;
counter_rd <= low_level;
---------------
rg_read_or_write <= low_level;
rg_write_on_FTDI <= '0';
----------
elsif clk_en = '1' then
----------
cur_state <= next_state;
---------------
rg_valid <= N_valid;
---------------
rg_address <= N_address;
---------------
if N_write_to_m = '0' then
counter_wr <= counter_wr+1;
else counter_wr <= counter_wr;
end if;
---------------
if count = '1' then
counter_rd <= counter_rd+1;
rg_write_on_FTDI <= '1';
else counter_rd <= counter_rd;
rg_write_on_FTDI <= rg_write_on_FTDI;
end if;
---------------
rg_read_from_m <= N_read_from_m;
rg_write_to_m <= N_write_to_m;
---------------
rg_read_or_write <= read_or_write;
----------
else
----------
cur_state <= cur_state;
---------------
rg_valid <= rg_valid;
---------------
rg_read_from_m <= rg_read_from_m;
rg_write_to_m <= rg_write_to_m;
---------------
counter_wr <= counter_wr;
counter_rd <= counter_rd;
---------------
rg_address <= rg_address;
---------------
rg_read_or_write <= rg_read_or_write;
rg_write_on_FTDI <= rg_write_on_FTDI;
----------
end if;
end if;
end process;
--============================================================
--============================================================
