плавая пауза между байтами думаю не проблема, главное что бы минимальная пауза была регулируемая в понятных приделах
Тогда вот:
CODE
//-----------------------------------------------------------------------------
// void __inline init_SPI2(void)
//-----------------------------------------------------------------------------
void __inline init_SPI2(void)
{
SPI2->CR1 =
(0 << SPI_CR1_SPE)
| (0 << SPI_CR1_DFF)
| (1 << SPI_CR1_SSM)
| (1 << SPI_CR1_SSI)
| (1 << SPI_CR1_MSTR)
| (2 << SPI_CR1_BR);
SPI2->CR2 =
(0 << SPI_CR2_RXNEIE)
| (0 << SPI_CR2_TXDMAEN)
| (1 << SPI_CR2_SSOE);
SPI2->CR1 =
(1 << SPI_CR1_SPE)
| (0 << SPI_CR1_DFF)
| (1 << SPI_CR1_SSM)
| (1 << SPI_CR1_SSI)
| (1 << SPI_CR1_MSTR)
| (2 << SPI_CR1_BR);
}
//-----------------------------------------------------------------------------
// void __inline init_TIMER3(void)
//-----------------------------------------------------------------------------
void __inline init_TIMER3(void)
{
TIM3->PSC = 0;
TIM3->CR1 = 0;
TIM3->ARR = 147 - 1; // ПЕРИОД СЛЕДОВАНИЯ ТУТ
TIM3->CCR1 = 10; // для отладки "желтый фронт"
TIM3->CCR4 = 1;
TIM3->CCMR1 = (OC_MODE_PWM1 << TIM_CCMR1_OC1M);
TIM3->CCER = (1 << TIM_CCER_CC1E) | (1 << TIM_CCER_CC4E);
TIM3->SMCR = 0;
TIM3->DIER =
(0 << TIM_DIER_CC1IE)
| (0 << TIM_DIER_CC4DE)
| (0 << TIM_DIER_UIE);
}
Еще нужно разрешить прерывание для DMA1_Stream3.
void DMA1_Stream3_IRQHandler(void) __attribute__((interrupt("IRQ")));
void DMA1_Stream3_IRQHandler(void)
{
if(DMA1->LISR & (1 << 27))
{
TIM3->CR1 = 0;
GPIOB->BSRRL = (1 << 12); // NSS=1
DMA1->LIFCR = (1 << 27);
}
}
Запускаем так:
TIM3->CR1 = 0;
TIM3->CNT = 0;
TIM3->DIER =
(0 << TIM_DIER_CC1IE)
| (0 << TIM_DIER_CC4DE)
| (0 << TIM_DIER_UIE);
SPI2->CR2 =
(0 << SPI_CR2_RXNEIE)
| (0 << SPI_CR2_TXDMAEN)
| (0 << SPI_CR2_RXDMAEN)
| (1 << SPI_CR2_SSOE);
DMA1->LIFCR = 0x0F7D0000;
DMA1_Stream2->CR =
(2 << DMA_SCR_PL)
| (5 << DMA_SCR_CHSEL)
| (1 << DMA_SCR_MINC)
| (1 << DMA_SCR_DIR)
| (0 << DMA_SCR_EN);
DMA1_Stream2->PAR = (DWORD)&SPI2->DR;
DMA1_Stream2->M0AR = (DWORD)&spi_tx[0];
DMA1_Stream2->NDTR = SPI_DATA_SIZE;
DMA1_Stream2->CR =
(2 << DMA_SCR_PL)
| (5 << DMA_SCR_CHSEL)
| (1 << DMA_SCR_MINC)
| (1 << DMA_SCR_DIR)
| (1 << DMA_SCR_EN);
DMA1_Stream3->CR =
(3 << DMA_SCR_PL)
| (0 << DMA_SCR_CHSEL)
| (1 << DMA_SCR_MINC)
| (0 << DMA_SCR_DIR)
| (0 << DMA_SCR_EN)
| (1 << DMA_SCR_TCIE);
DMA1_Stream3->PAR = (DWORD)&SPI2->DR;
DMA1_Stream3->M0AR = (DWORD)&spi_rx[0];
DMA1_Stream3->NDTR = SPI_DATA_SIZE;
DMA1_Stream3->CR =
(3 << DMA_SCR_PL)
| (0 << DMA_SCR_CHSEL)
| (1 << DMA_SCR_MINC)
| (0 << DMA_SCR_DIR)
| (1 << DMA_SCR_EN)
| (1 << DMA_SCR_TCIE);
GPIOB->BSRRH = (1 << 12);
SPI2->CR2 =
(0 << SPI_CR2_RXNEIE)
| (0 << SPI_CR2_TXDMAEN)
| (1 << SPI_CR2_RXDMAEN)
| (1 << SPI_CR2_SSOE);
TIM3->DIER =
(0 << TIM_DIER_CC1IE)
| (1 << TIM_DIER_CC4DE)
| (0 << TIM_DIER_UIE);
TIM3->CR1 = (1 << TIM_CR1_CEN);