library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity matrix_transposition is
    generic (
        N_ROWS : integer := 64;
        N_COLS : integer := 46            
    );
    port (
        clk : in std_logic;
        reset : in std_logic;
        din : in std_logic;
        din_valid : in std_logic;
        dout : out std_logic;
        dout_valid : out std_logic
        
       ; rd_addr_out : out integer
       ; rd_addr_v1_out : out integer
       ; rd_addr_v2_out : out integer
       ; wr_addr_out : out integer
       ; ready_out : out std_logic        
    );
end matrix_transposition;

architecture RTL of matrix_transposition is
    constant SIZE : integer := N_ROWS * N_COLS;
    constant HI : integer := SIZE - 1;
    
    signal buf1 : std_logic_vector(HI downto 0);
    signal buf2 : std_logic_vector(HI downto 0);    
    signal wr_addr : integer range 0 to HI := 0;
    signal rd_addr : integer range 0 to HI := 0;
    signal row_no : integer range 0 to N_ROWS-1 := 0;
    signal col_no : integer range 0 to N_COLS-1 := 0;
    signal buf_mux : std_logic := '0';  
    signal full : std_logic := '0';
begin

    process(clk)
    begin
        if rising_edge(clk) then
            if din_valid = '1' then                
                
                if buf_mux = '0' then
                    buf1(wr_addr) <= din;
                else    
                    buf2(wr_addr) <= din;
                end if;
                
                if wr_addr = HI then
                    wr_addr <= 0;        
                else
                    wr_addr <= wr_addr + 1;
                end if;
                
                if wr_addr = HI then
                    buf_mux <= not(buf_mux);
                    full <= '1';
                end if;
                
                
                if row_no = N_ROWS-1 then
                    row_no <= 0;
                    
                    if col_no = N_COLS-1 then
                        col_no <= 0;                        
                    else
                        col_no <= col_no + 1;                        
                    end if;
                else                    
                    row_no <= row_no + 1;                    
                end if;
                
                
                if row_no = N_ROWS-1 then                    
                    if col_no = N_COLS-1 then                        
                        rd_addr <= 0;
                    else                        
                        rd_addr <= col_no + 1;
                    end if;
                else
                    rd_addr <= rd_addr + N_COLS;
                end if;
                
            end if;
            
            if buf_mux = '1' then
                dout <= buf1(rd_addr);
            else
                dout <= buf2(rd_addr);
            end if;
            
            dout_valid <= din_valid and full;                
        end if;
    end process;
      

    rd_addr_out <= rd_addr;
--    rd_addr_v1_out <= rd_addr_v1;
--    rd_addr_v2_out <= rd_addr_v2;
    wr_addr_out <= wr_addr;
    ready_out <= full;
        

end RTL;

rd_addr_out : out integer
      ; rd_addr_v1_out : out integer
      ; rd_addr_v2_out : out integer
      ; wr_addr_out : out integer

    ...

     signal dout1 : std_logic;
     signal dout2 : std_logic;
begin
     process(clk)
    begin
        if rising_edge(clk) then
          
      ...
     if buf_mux = '1' then
          dout1 <= buf1(rd_addr);
     else
          dout2 <= buf2(rd_addr);
     end if;
        ...
        end if;
    end process;

dout <= dout1 when buf_mux = '1' else dout2;

end RTL;

rd_addr_out : out integer
     ; rd_addr_v1_out : out integer
     ; rd_addr_v2_out : out integer
     ; wr_addr_out : out integer