Код
ARM Cortex-M3 Processor
Revision: r2p1
Technical Reference Manual
Neighboring load and store single instructions can pipeline their address and data phases. This enables these instructions to complete in a single execution cycle.
ARM Cortex-M4 Processor
Revision: r0p1
Technical Reference Manual
Neighboring load and store single instructions can pipeline their address and data phases but in some cases, such as 32-bit opcodes aligned on odd halfword boundaries, they might not pipeline optimally.
Revision: r2p1
Technical Reference Manual
Neighboring load and store single instructions can pipeline their address and data phases. This enables these instructions to complete in a single execution cycle.
ARM Cortex-M4 Processor
Revision: r0p1
Technical Reference Manual
Neighboring load and store single instructions can pipeline their address and data phases but in some cases, such as 32-bit opcodes aligned on odd halfword boundaries, they might not pipeline optimally.
Оказывается у М3 и М4 разная растактовка LDR/STR. У М4 ARM-ом заложено что-то немного похожее на обозначенную мной особенность большинства М0-процов производителя NXP. Чья это фича - ещё туманней стало.