enum DMA_ISR { DMA_ISR_FEIF = 0,   DMA_ISR_DMEIF = 2,    DMA_ISR_TEIF,  DMA_ISR_HTIF,  DMA_ISR_TCIF,
               DMA_ISR_FEIF0 = 0,  DMA_ISR_DMEIF0  = 2,  DMA_ISR_TEIF0, DMA_ISR_HTIF0, DMA_ISR_TCIF0,
               DMA_ISR_FEIF1,      DMA_ISR_DMEIF1  = 8,  DMA_ISR_TEIF1, DMA_ISR_HTIF1, DMA_ISR_TCIF1, };


#define ISR_ALL_FLAGS ((1<<DMA_ISR_FEIF)|(1<<DMA_ISR_DMEIF)|(1<<DMA_ISR_TEIF)|(1<<DMA_ISR_HTIF)|(1<<DMA_ISR_TCIF))


enum DMA_FIFO_TRESHOLD { DMA_DIRECT_MODE = 0, DMA_FIFO_1QTR_FULL, DMA_FIFO_HALF_FULL, DMA_FIFO_3QTR_FULL, DMA_FIFO_FULL };

#define DMA_FIFO_LESS_1QTR_FULL  
#define DMA_FIFO_LESS_HALF_FULL DMA_SxFCR_FS_0
#define DMA_FIFO_LESS_3QTR_FULL DMA_SxFCR_FS_1
#define DMA_FIFO_OVER_3QTR_FULL (DMA_SxFCR_FS_0 + DMA_SxFCR_FS_1)
#define DMA_FIFO_IS_EMPTY       DMA_SxFCR_FS_2
#define DMA_FIFO_IS_FULL        (DMA_SxFCR_FS_0 + DMA_SxFCR_FS_2)

#define DMA_FIFO_TH_1QTR_FULL   0
#define DMA_FIFO_TH_HALF_FULL   DMA_SxFCR_FTH_0
#define DMA_FIFO_TH_3QTR_FULL   DMA_SxFCR_FTH_1
#define DMA_FIFO_TH_FULL        DMA_SxFCR_TH

typedef struct {
  uint8_t threshold       : 2;
  uint8_t direct_mode_dis : 1;
  uint8_t status          : 3;
} dma_fifo_s;