#define USE_STATUS_REG 0   //doesn't help any way

void LOGGER_PageWrite(uint32_t address, uint32_t length, uint8_t *buffer)
{
    #if USE_STATUS_REG
    uint32_t timer;
    #endif
    volatile uint32_t page_limit=0;
    volatile uint32_t bytes_to_fit=0;
    volatile uint32_t bytes_to_write=0;

    //find a page limit for the address
    while (address > page_limit)
    {
        page_limit += 64;
    }
    //actual page limit
    page_limit--;

    bytes_to_fit = page_limit - address;
    bytes_to_write = bytes_to_fit;

    // Note!!!Every write operation demands a write enable!!!
    SPI_CSlow();
    SPI_SendByte(SPIEEPROM_CMD_WREN);
    SPI_CShigh();

    // start write
    SPI_CSlow();
    // send write command
    SPI_SendByte(SPIEEPROM_CMD_WRITE);
    // send address
    SPI_SendByte(address>>8);
    SPI_SendByte(address&0x00FF);
    while(bytes_to_write--)
    {
        // send data to be written
         SPI_SendByte(*buffer++);
    }
    // stop write
    SPI_CShigh();

    #if USE_STATUS_REG
    timer = LOGGER_DELAY;
    //wait for write operation to complete
    while(SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP)
    {
        if(!--timer)
           break;
    }
    #else
    //needs 5ms for page write
    Delay_us_sys(5000);
    #endif

    if (bytes_to_fit <= length)
    {
        address += bytes_to_fit+1;
        bytes_to_write = length - bytes_to_fit;

         // Note!!!Every write operation demands a write enable!!!
        SPI_CSlow();
        SPI_SendByte(SPIEEPROM_CMD_WREN);
        SPI_CShigh();

        // start write
        SPI_CSlow();
        // send write command
        SPI_SendByte(SPIEEPROM_CMD_WRITE);
        // send address
        SPI_SendByte(address>>8);
        SPI_SendByte(address&0xFF);
        while(bytes_to_write--)
        {
            // send data to be written
            SPI_SendByte(*buffer++);
        }
        // stop write
        SPI_CShigh();

        #if USE_STATUS_REG
        timer = LOGGER_DELAY;
        //wait for write operation to complete
        while(SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP)
        {
            if(!--timer)
                break;
        }
        #else
        //needs 5ms for page write
        Delay_us_sys(5000);
        #endif
    }
}

uint8_t rxbuffer[50];
for (int i=0; i < 50; i++)
{
    rxbuffer[i] = i+1;
}
LOGGER_PageWrite(80, 50, rxbuffer);

uint8_t txbuffer[50];
LOGGER_Read(80, 50,txbuffer);

void eep_write(uint32_t addr, uint32_t len, uint8_t *data)
{
    uint32_t bytes_to_write;

    while(len)
    {
        if(((addr & (EEPROM_PAGE_SIZE - 1)) + len) >= EEPROM_PAGE_SIZE)
            bytes_to_write = EEPROM_PAGE_SIZE - (addr & (EEPROM_PAGE_SIZE - 1));
        else
            bytes_to_write = len;

        // тут пишем (addr, bytes_to_write, data);

        data += a;
        addr += a;
        len -= a;
    }
}

data += a;
addr += a;
len -= a;

void LOGGER_Write(uint32_t address, uint32_t lenght, uint8_t *data)
{
        uint32_t timer;
    uint32_t bytes_to_write=0;

    while(lenght)
    {
       if(((address & (PAGE_SIZE - 1)) + lenght) >= PAGE_SIZE)
           bytes_to_write = PAGE_SIZE - (address & (PAGE_SIZE - 1));
       else
          bytes_to_write = lenght;

       // Every write operation demands a write enable!!!
          SPI_CSlow();
          SPI_SendByte(SPIEEPROM_CMD_WREN);
          SPI_CShigh();

          // start write
          SPI_CSlow();
          // send write command
          SPI_SendByte(SPIEEPROM_CMD_WRITE);
          // send address
          SPI_SendByte(address>>8);
          SPI_SendByte(address&0x00FF);

          while(lenght--)
          {
              // send data to be written
               SPI_SendByte(*data++);
          }
          // stop write
          SPI_CShigh();

          timer = LOGGER_DELAY;
          //wait for write operation to complete
          while(SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP)
          {
              if(!--timer)
                  break;
          }
      
       data += bytes_to_write;
       address += bytes_to_write;
       lenght -= bytes_to_write;
    }
}

Default_Handler:
  b  Default_Handler

  .size  Default_Handler, .-Default_Handler

void eep_write(uint32_t addr, uint32_t len, uint8_t *data)
{
  uint32_t i;
  while (len) {
    i = EEPROM_PAGE_SIZE - (addr & EEPROM_PAGE_SIZE - 1);
    if (i > len) i = len;
    //тут проверяем статус EEPROM, посылаем WREN и пишем (addr, i, data);
    data += i;
    addr += i;
    len -= i;
  }
}

void LOGGER_Write(uint32_t address, uint32_t lenght, uint8_t *data)
{
    uint32_t timer;
    uint32_t bytes_to_write=0;

    while(lenght)
    {
       if(((address & (PAGE_SIZE - 1)) + lenght) >= PAGE_SIZE)
          bytes_to_write = PAGE_SIZE - (address & (PAGE_SIZE - 1));
       else
          bytes_to_write = lenght;

       // Every write operation demands a write enable!!!
       SPI_CSlow();
       SPI_SendByte(SPIEEPROM_CMD_WREN);
       SPI_CShigh();

       // start write
       SPI_CSlow();
       // send write command
       SPI_SendByte(SPIEEPROM_CMD_WRITE);
       // send address
       SPI_SendByte(address>>8);
       SPI_SendByte(address&0x00FF);

       address += bytes_to_write;
       lenght -= bytes_to_write;

       while(bytes_to_write--)
       {
           // send data to be written
            SPI_SendByte(*data++);
       }
       // stop write
       SPI_CShigh();

       timer = LOGGER_DELAY;
       //wait for write operation to complete
       while(SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP)
       {
           if(!--timer)
               break;
       }
    }
}

while(SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP)
{
    if(!--timer)
          break;
}

// commands
#define SPIEEPROM_CMD_READ        0x03    // Read byte(s)
#define SPIEEPROM_CMD_WRITE        0x02    // Write byte(s)
#define SPIEEPROM_CMD_WREN        0x06    // Write Enable
#define SPIEEPROM_CMD_WRDI        0x04    // Write Disable
#define SPIEEPROM_CMD_RDSR        0x05    // Read Status Register
#define SPIEEPROM_CMD_WRSR        0x01    // Write Status Register

// status register bit defines
#define SPIEEPROM_STATUS_WIP    0x01    // Write in progress
#define SPIEEPROM_STATUS_WEL    0x02    // Write enable
#define SPIEEPROM_STATUS_BP0    0x04    // Block Protection 0
#define SPIEEPROM_STATUS_BP1    0x08    // Block Protection 1
#define SPIEEPROM_STATUS_WPEN    0x80    // Write Protect Enable

uint32_t SPI_TransferByte(uint32_t sendbyte)
{
    uint32_t timeout = SPI_DELAY;
    /* Check that transmit buffer is empty */
    while (!(SPI_USART->STATUS & USART_STATUS_TXBL))
    {
        if(!--timeout)
            break;
    }
    SPI_USART->TXDATA = (uint32_t)sendbyte;
    /* Wait for transmitting to finished */
    timeout = SPI_DELAY;
    while (!(SPI_USART->STATUS & USART_STATUS_TXC))
    {
        if(!--timeout)
            break;
    }
    //return data;
    return majority32const(&SPI_USART->RXDATA);
}

void SPI_SendByte(uint8_t sendbyte)
{
    uint32_t timeout = SPI_DELAY;

    USART_Tx(SPI_USART,sendbyte);

    /* Wait for transmitting to finished */
    while (!(SPI_USART->STATUS & USART_STATUS_TXC))
    {
      if(!--timeout)
          break;
    }
}

uint8_t SPIEEPROM_ReadStatus(void)
{
    uint8_t status;
    SPI_CSlow();
    // send read status register command
    SPI_SendByte(SPIEEPROM_CMD_RDSR);
    // get status register value
    status = SPI_TransferByte(0xFF);
    SPI_CShigh();
    return status;
}

while(SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP)
{
  //NO TIMEOUT
}

Delay_us(5000);

tWC (Note 13)   Write Cycle Time    5 ms .

13.tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.

busy = 1;
//wait for write operation to complete
while(busy)
{
    busy = (SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP);
}

busy = 1;
//wait for write operation to complete
while(busy)
{
    busy = (SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP);
    Delay_us(1);
}

uint8_t SPIEEPROM_ReadStatus(void)
{
    uint8_t status;
    //SPI_CSlow();  //outside

    // send read status register command
    //SPI_SendByte(SPIEEPROM_CMD_RDSR);  //transfer - not send
    SPI_TransferByte(SPIEEPROM_CMD_RDSR);

    // get status register value
    status = SPI_TransferByte(0xFF);

    //SPI_CShigh();  //outside

    return status;
}

busy = 1;
//wait for write operation to complete
SPI_CSlow();
while(busy)
{
    busy = (SPIEEPROM_ReadStatus() & SPIEEPROM_STATUS_WIP);
}
SPI_CShigh();