int cnt1, cnt2, cnt3;

/*
* Прерывание таймера 1 (14)
* Смещение в таблице векторов 0x40 + 14 * 4 = 0x78
*/
void Vector78(void) {

cnt1 += 1;

MDR_TIMER1->STATUS = (uint32_t) 0;

}

/*
* Прерывание таймера 2 (15)
* Смещение в таблице векторов 0x40 + 15 * 4 = 0x7C
*/
void Vector7C(void) {

cnt2 += 1;

MDR_TIMER2->STATUS = (uint32_t) 0;

}

/*
* Прерывание таймера 3 (16)
* Смещение в таблице векторов 0x40 + 16 * 4 = 0x80
*/
void Vector80(void) {

cnt3 += 1;

MDR_TIMER3->STATUS = (uint32_t) 0;

}

int main(void) {

int cnt4 = 0;
cnt1 = cnt2 = cnt3 = 0;

... Код включения тактирования ядра и таймеров в другом модуле ...

MDR_TIMER1->CNTRL = (uint32_t) 0;
MDR_TIMER1->CNT = (uint32_t) 0;
MDR_TIMER1->PSG = (uint32_t) 0;
MDR_TIMER1->ARR = (uint32_t) 4095;
MDR_TIMER1->IE = TIMER_IE_CNT_ARR_EVENT_IE | TIMER_IE_CNT_ZERO_EVENT_IE;
MDR_TIMER1->STATUS = (uint32_t) 0;
MDR_TIMER1->CNTRL = (uint32_t) 1;

MDR_TIMER3->CNTRL = (uint32_t) 0;
MDR_TIMER3->CNT = (uint32_t) 0;
MDR_TIMER3->PSG = (uint32_t) 0;
MDR_TIMER3->ARR = (uint32_t) 4095;
MDR_TIMER3->IE = TIMER_IE_CNT_ARR_EVENT_IE | TIMER_IE_CNT_ZERO_EVENT_IE;
MDR_TIMER3->STATUS = (uint32_t) 0;
MDR_TIMER3->CNTRL = (uint32_t) 1;

MDR_TIMER2->CNTRL = (uint32_t) 0;
MDR_TIMER2->CNT = (uint32_t) 0;
MDR_TIMER2->PSG = (uint32_t) 0;
MDR_TIMER2->ARR = (uint32_t) 4095;
MDR_TIMER2->IE = TIMER_IE_CNT_ARR_EVENT_IE | TIMER_IE_CNT_ZERO_EVENT_IE;
MDR_TIMER2->STATUS = (uint32_t) 0;
MDR_TIMER2->CNTRL = (uint32_t) 1;

NVIC_EnableIRQ(TIMER1_IRQn);
NVIC_EnableIRQ(TIMER2_IRQn);
NVIC_EnableIRQ(TIMER3_IRQn);

while (true) {
cnt4 += 1;
}
}

(gdb) p *0x40070000 // Регистр TIMER1->CNT
$82 = 3285
$83 = 1406
$84 = 2573
$85 = 1891

(gdb) p Vector78
$86 = {void (void)} 0x300 <Vector78>
(gdb) p *0x00000078
$87 = 769 // 0x300 == (769 & 1)

(gdb) p *0x40070058 // Регистр TIMER1->IE
$88 = 3 // Прерывания по 0 и по ARR разрешены
(gdb) p *0x40070054 // Регистр TIMER1->STATUS
$89 = 3 // Оба события

(gdb) p *0xE000E100
$90 = 114688 // Биты 14,15,16

static dmaCtrlData_t dmaCtrlData[16]
__attribute__((aligned(512), section("ahb_lite")));
volatile char tmp1[] = "DMA test string.";
volatile char tmp2[20];

int main(void) {

... инициализация клоков ...

memset(dmaCtrlData, 0x0, sizeof(dmaCtrlData));

// Reset to the initial state.
MDR_DMA->CTRL_BASE_PTR = (uint32_t) dmaCtrlData;
MDR_DMA->CFG = 1U;
MDR_DMA->CHNL_SW_REQUEST = 0U;
MDR_DMA->CHNL_PRI_ALT_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_PRIORITY_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_REQ_MASK_SET = 0xFFFFFFFF;
MDR_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
MDR_DMA->CHNL_ENABLE_CLR = 0xFFFFFFFF;
MDR_DMA->ERR_CLR = 1U;

// Configure DMA_CH0
dmaCtrlData[0].dmaSrcEndAddr = (uint32_t) tmp1 + sizeof(tmp1) - 1;
dmaCtrlData[0].dmaDstEndAddr = (uint32_t) tmp2 + sizeof(tmp1) - 1;
dmaCtrlData[0].dmaControl = (0x00 << 30) | // One byte destination increment;
(0x00 << 28) | // Destination transfer unit size;
(0x00 << 26) | // One byte source increment;
(0x00 << 24) | // Source transfer unit size;
(0U << 21) | // dst_prot_ctrl (whatever this is - let it be 0);
(0U << 18) | // src_prot_ctrl;
(15U << 14) | // Acquire the bus and do not release until the transfer complete;
((sizeof(tmp1) - 1) << 4) |
// Transfers count - 1.
(0U << 3) | // next_useburst ??
(1U << 0); // Simple request mode. Auto-request mode does not work either.
MDR_DMA->CHNL_REQ_MASK_CLR = 1U;
MDR_DMA->CHNL_ENABLE_SET = 1U;
MDR_DMA->CHNL_SW_REQUEST = 1U;

... зацикливаемся ...
}

{ STATUS = 0x101f0001,
CFG = 0x0,
CTRL_BASE_PTR = 0x20100000,
ALT_CTRL_BASE_PTR = 0x20100200,
WAITONREQ_STATUS = 0x7fffffff,
CHNL_SW_REQUEST = 0x0,
CHNL_USEBURST_SET = 0x0,
CHNL_USEBURST_CLR = 0x0,
CHNL_REQ_MASK_SET = 0xfffffffe,
CHNL_REQ_MASK_CLR = 0xfffffffe,
CHNL_ENABLE_SET = 0x1,
CHNL_ENABLE_CLR = 0x1,
CHNL_PRI_ALT_SET = 0x0,
CHNL_PRI_ALT_CLR = 0x0,
CHNL_PRIORITY_SET = 0x0,
CHNL_PRIORITY_CLR = 0x0,
RESERVED0 = {0x0, 0x0, 0x0},
ERR_CLR = 0x0 }

{ dmaSrcEndAddr = 0x20000614,
dmaDstEndAddr = 0x20005588,
dmaControl = 0x3c101,
dmaUnused = 0x0 }

{ STATUS = 0x101f0001,
CFG = 0x0,
CTRL_BASE_PTR = 0x20100000,
ALT_CTRL_BASE_PTR = 0x20100200,
WAITONREQ_STATUS = 0x7fffffff,
CHNL_SW_REQUEST = 0x0,
CHNL_USEBURST_SET = 0x0,
CHNL_USEBURST_CLR = 0x0,
CHNL_REQ_MASK_SET = 0xfffffffe,
CHNL_REQ_MASK_CLR = 0xfffffffe,
CHNL_ENABLE_SET = 0x0,
CHNL_ENABLE_CLR = 0x0,
CHNL_PRI_ALT_SET = 0x0,
CHNL_PRI_ALT_CLR = 0x0,
CHNL_PRIORITY_SET = 0x0,
CHNL_PRIORITY_CLR = 0x0,
RESERVED0 = {0x0, 0x0, 0x0},
ERR_CLR = 0x0 }

{ dmaSrcEndAddr = 0x20000614,
dmaDstEndAddr = 0x20005588,
dmaControl = 0x3c000,
dmaUnused = 0x0 }

(volatile char (*)[17]) 0x20000604 <tmp1>
(volatile char (*)[20]) 0x20005578 <tmp2>
(dmaCtrlData_t (*)[16]) 0x20100000 <dmaCtrlData>