/*!< SPI Config */
  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
  SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
  SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
  SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
  SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
  SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32;  //APB1=36Mhz => ~1Mhz //APB2=72Mhz                                                                  
  SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
  SPI_InitStructure.SPI_CRCPolynomial = 7;
  SPI_Init(SPIx, &SPI_InitStructure);

uint32_t SPI_TransferByte(SPI_TypeDef *SPIx, uint8_t data)
{
    uint32_t timeout;

    // All data transmitted/received but SPI may be busy so wait until done.
    timeout = SPI_DELAY;
    while (SPIx->SR & SPI_I2S_FLAG_BSY) { if(!timeout--) return SPI_ERR; }

    // Setting the Data Register (DR) transmits the byte of data on MOSI.
    SPIx->DR = data;

    //  Wait for any data on MISO pin to be received.
    timeout = SPI_DELAY;
    while (!(SPIx->SR & SPI_I2S_FLAG_RXNE)) { if(!timeout--) return SPI_ERR; }

    //  Return the data received on MISO pin.
    return (uint8_t)(SPIx->DR);
}

typedef struct
{
  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
  union
  {
    __IO uint16_t DR16;   /*!< SPI data register,                                   Address offset: 0x0C */
    __IO uint8_t DR8;     /*!< SPI data register,                                   Address offset: 0x0C */
  };
  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */
  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
} SPI_TypeDef;

void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
{
  uint32_t spixbase = 0x00;

  /* Check the parameters */
  assert_param(IS_SPI_ALL_PERIPH(SPIx));

  spixbase = (uint32_t)SPIx;
  spixbase += 0x0C;
  
  *(__IO uint8_t *) spixbase = Data;
}

When the SPIx_DR register is accessed, data frames are always right-aligned
into either a byte (if the data fits into a byte) or a half-word (see Figure 388). During
communication, only bits within the data frame are clocked and transferred.

uint32_t spixbase = 0x00;

  spixbase = (uint32_t)SPIx;
  spixbase += 0x0C;

  *(__IO uint8_t *) spixbase = Data;

#define SPI_SendData8(SPIx, data)   *(__IO uint8_t *)&SPIx->DR = data

  SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
  SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
...

typedef struct s_param
{
    int    v_int;
} __attribute__((packed)) s_param;
...
((s_param *)&out[p_out])->v_int += (in[p_in] - '0');

#define USIC_CH_RBCTR_DPTR_Pos
#define USIC_CH_RBCTR_DPTR_Msk
#define USIC_CH_RBCTR_LIMIT_Pos
#define USIC_CH_RBCTR_LIMIT_Msk
#define USIC_CH_RBCTR_SRBTM_Pos
#define USIC_CH_RBCTR_SRBTM_Msk
#define USIC_CH_RBCTR_SRBTEN_Pos
#define USIC_CH_RBCTR_SRBTEN_Msk
#define USIC_CH_RBCTR_SRBINP_Pos
#define USIC_CH_RBCTR_SRBINP_Msk
#define USIC_CH_RBCTR_ARBINP_Pos
#define USIC_CH_RBCTR_ARBINP_Msk
#define USIC_CH_RBCTR_RCIM_Pos
#define USIC_CH_RBCTR_RCIM_Msk
#define USIC_CH_RBCTR_SIZE_Pos
#define USIC_CH_RBCTR_SIZE_Msk
#define USIC_CH_RBCTR_RNM_Pos
#define USIC_CH_RBCTR_RNM_Msk
#define USIC_CH_RBCTR_LOF_Pos
#define USIC_CH_RBCTR_LOF_Msk
#define USIC_CH_RBCTR_ARBIEN_Pos
#define USIC_CH_RBCTR_ARBIEN_Msk
#define USIC_CH_RBCTR_SRBIEN_Pos
#define USIC_CH_RBCTR_SRBIEN_Msk
#define USIC_CH_RBCTR_RBERIEN_Pos
#define USIC_CH_RBCTR_RBERIEN_Msk

      io->RBCTR = ch + UART_FIFO_TX_SIZE |
      UART_FIFO_RX_SIZE / 2 - 1 << 8 | (srTxRxErr & 7 << 3) << 16 - 3 |
      srTxRxErr >> 6 << 19 | 3 << 22 |
      concat(USIC_FIFO_SIZE_, UART_FIFO_RX_SIZE) << 24 |
      B15 | B28 | B30 | B31;

typedef __packed u16 u16p8;
typedef __packed s16 s16p8;
typedef __packed u32 u32p8;
typedef __packed s32 s32p8;
typedef __packed u64 u64p8;
typedef __packed s64 s64p8;
typedef __packed u32 u32p16;
typedef __packed s32 s32p16;
typedef __packed u64 u64p16;
typedef __packed s64 s64p16;
typedef __packed u64 u64p32;
typedef __packed s64 s64p32;