/*****************************************************************************
Биты регистра состояния
******************************************************************************/

/* Bit 7 = "1" (RDY) indicates the device is ready.
Bit 7 = "0" indicates the write cycle is in progress. */
#define AT45_SREG_RDY  7



/* Bit 6 = "0" data in the main memory page matches the data in the buffer.
Bit 6 = "1" at least one bit of the data in the main memory page not match
the data in the buffer. */
#define AT45_SREG_COMP  6



/* маска идентификатора чипа, сдвинутая в право на два бита */
#define AT45_DEVICE_ID_MASK (0x0F << 2)



/*****************************************************************************
Инициализация SPI драйвера и тестирование МС памяти
Возвращает TRUE, если нет ошибок памяти, иначе FALSE
******************************************************************************/
BOOL SPIMEM_Init(void)
{
   SPI_Init(); /* инициализируем порт SPI */

    

/* ждем установки памяти в рабочее состояние */
ULONG start = g_SysTIME_ms;
    while(AT45_STARTUP_TIME > (g_SysTIME_ms - start));

    

/* читаем регистр статуса МС */
    UCHAR status = SPIMEM_GetStatus();
    if(AT45_DEVICE_ID != (status  & AT45_DEVICE_ID_MASK))
       return FALSE; /* ошибка! не совпал ID установленной МС */

    

/* тестируем внутренние буферы МС */
UCHAR test = 0x55; /* тест-байт */
    for(UCHAR j = 0; j < 2; j++)
    {
     for(UINT i = 0; i < AT45_PAGE_SIZE; i++)
     {
           /* пишем тест-байт в оба буфера */
           SPIMEM_BufWrite(AT45_BUFFER1_WRITE, i, 1, &test);
         SPIMEM_BufWrite(AT45_BUFFER2_WRITE, i, 1, &test);
      
            /* проверяем прочитанный байт на равенство тест-байту */
        SPIMEM_BufRead(AT45_BUFFER1_READ, i, 1, &status);
         if(test != status)
                return FALSE;
            SPIMEM_BufRead(AT45_BUFFER2_READ, i, 1, &status);
         if(test != status)
              return FALSE;
        }
        test = 0xAA; /* инвертируем тест-байт */
    }

    /* OK */
    return TRUE;
}



/*****************************************************************************
Чтение регистра статуса
AT45_STATUS_READ
******************************************************************************/
UCHAR SPIMEM_GetStatus(void)
{
   SPI_SlaveSelect(); /* выбираем чип */
    SPI_Write(AT45_STATUS_READ); /* посылаем команду */
    UCHAR status = SPI_Read(); /* читаем статус */
    SPI_SlaveDeselect(); /* освобождаем чип */
    return status;
}


/*****************************************************************************
Чтение порта SPI
******************************************************************************/
UCHAR SPI_Read(void)
{
   SPDR = 0xff; /* загружаем SPI данными */
    while(!(SPSR & (1<<SPIF))); /* ждем окончания передачи */
    return SPDR; /* возвращаем принятые данные */
}

/*****************************************************************************
Запись в порт SPI
******************************************************************************/
void SPI_Write(UCHAR data)
{
   SPDR = data; /* загружаем SPI данными */
    while(!(SPSR & (1<<SPIF))); /* ждем окончания передачи */
}



/*****************************************************************************
Чтение буфера
AT45_BUFFER1(2)_READ = 0x54(0x56)
Вход:
command - команда чтения буфера №1 или №2
buf_pos - адрес начала читаемого блока в буфере
size  - размер блока
trg  - буфер для записи
******************************************************************************/
void SPIMEM_BufRead(UCHAR command, UINT buf_pos, UINT size, UCHAR *trg)
{
   /* сылаем команду */
   SPIMEM_Tx5(command, 0, buf_pos);

    /* читаем массив */
    while(size--)
     *trg++ = SPI_Read();

    /* освобождаем чип */
    SPI_SlaveDeselect();
}

/*****************************************************************************
Запись в буфер
AT45_BUFFER1(2)_WRITE = 0x84(0x87)
Вход:
command - команда записи в буфер №1 или №2
buf_pos - адрес начала читаемого блока в буфере
size  - размер блока
src  - буфер для чтения
******************************************************************************/
void SPIMEM_BufWrite(UCHAR command, UINT buf_pos, UINT size, UCHAR *src)
{
   /* посылаем команду */
   SPIMEM_Tx4(command, 0, buf_pos);

    /* пишем массив */
    while(size--)
     SPI_Write(*src++);

    /* освобождаем чип */
    SPI_SlaveDeselect();
}



/*****************************************************************************
4-х байтная посылка:
Вход:
command  - команда
page_addr - адрес страницы
buf_pos  - позиция в буфере

!!! Кроме этого производит выборку кристалла МС !!!
******************************************************************************/
void SPIMEM_Tx4(UCHAR command, UINT page_addr, UINT buf_pos)
{
   SPI_SlaveSelect();
   page_addr <<= 1;
    SPI_Write(command);
   SPI_Write(HIBYTE(page_addr));
    SPI_Write(LOBYTE(page_addr) | HIBYTE(buf_pos));
    SPI_Write(LOBYTE(buf_pos));
}

/*****************************************************************************
5-и байтная посылка:
Установка адреса дополняется посылкой 1-го пустого байта

!!! Кроме этого производит выборку кристалла МС !!!
******************************************************************************/
void SPIMEM_Tx5(UCHAR command, UINT page_addr, UINT buf_pos)
{
   SPIMEM_Tx4(command, page_addr, buf_pos);
    SPI_Write(0);
}

uint8_t spi_t::exchange(uint8_t out)
{
    uint8_t Data = out;
    for(uint8_t i = 0; i < 8; i++)
    {
        if(Data & (1 << 7))
            on(SPI_MOSI);
        else
            off(SPI_MOSI);

        on(SPI_SCLK);

        Data <<= 1;

        if(signal(SPI_MISO))
            Data |= (1<<0);
        off(SPI_SCLK);
    }
    return Data;
}
inline void spi_t::wait_done()
{
}
#define STATUS_READ                     0xD7

uint8_t at45_t::ReadStatus( void )
{
    Enable();
    spi_t::exchange(STATUS_READ);
    spi_t::wait_done();
    status_t Result = (status_t)spi_t::exchange();              //send dummy data and receive Status
    spi_t::wait_done();
    Disable();
    return Result;
}

#if     defined( AT45DB041 )
    #define FLASH_ID_MASK           0x38
    #define FLASH_ID                0x18
#elif   defined( AT45DB161 )
    #define FLASH_ID_MASK           0x3C
    #define FLASH_ID                0x2C
#elif   defined( AT45DB321 )
    #define FLASH_ID_MASK           0x3C
    #define FLASH_ID                0x34
#else
    #error  "No External flash type specified"
#endif
#define COMPARE_MISMATCH_BIT            (1<<6)
#define FLASH_READY_BIT                 (1<<7)

uint8_t at45_t::WaitReady(void)
{
    uint8_t Result;
    do
        Result = ReadStatus();
    while( (Result & (FLASH_ID_MASK | FLASH_READY_BIT)) != (FLASH_ID | FLASH_READY_BIT));
    return Result;
}

#define DF_CMD_STATUS_READ_SPI03            0xD7
unsigned char bLastStatus;

// *
// * additionally deactivates Chip Select signal before actual waiting,
// * places last status register value in bLastStatus
// *
void DF_Wait_Busy( void )
{
    DF_ChipSelect_Stop();
    bLastStatus = 0;
    DF_ChipSelect_Start();
    SPI_WriteByte( DF_CMD_STATUS_READ_SPI03 );
    do {
        bLastStatus = SPI_ReadByte();
    } while( (bLastStatus & 0x80) == 0 );
    DF_ChipSelect_Stop();
}

void DF_Wait_Busy( void )
{
    DF_ChipSelect_Stop();
    bLastStatus = 0;
    do {
        DF_ChipSelect_Start();
        SPI_WriteByte( DF_CMD_STATUS_READ_SPI03 );
        bLastStatus = SPI_ReadByte();
        DF_ChipSelect_Stop();
    } while( (bLastStatus & 0x80) == 0 );
}

#define SPI_MODE                0x38    // MSTR CPOL CPHA = 111
#define SPI_RATE                0x08

// SPI Initialization
void SPI_Init( void )
{
    S0SPSR;
    S0SPINT         = 0x01;
    S0SPCCR         = SPI_RATE;
    S0SPCR          = SPI_MODE;
    S0SPDR;
    S0SPSR;
}

// SPI Read byte
unsigned char SPI_ReadByte( void )
{
    unsigned char bTmp;

    S0SPSR;
    S0SPCCR         = SPI_RATE;
    S0SPCR          = SPI_MODE;
    S0SPDR          = 0;
    do {
        bTmp = S0SPSR;
        if( (bTmp & 0x10) != 0 )
            // if MODF = 1
            S0SPCR = SPI_MODE;
        if( (bTmp & 0x40) != 0 )
            // if WCOL = 1
            S0SPDR;
    } while( (bTmp & 0x80) == 0 );

    return( S0SPDR );
}

// SPI Write byte
void SPI_WriteByte( unsigned char bData )
{
    unsigned char bTmp;

    S0SPSR;
    S0SPCCR         = SPI_RATE;
    S0SPCR          = SPI_MODE;
    S0SPDR          = bData;
    do {
        bTmp = S0SPSR;
        if( (bTmp & 0x10) != 0 )
            // if MODF = 1
            S0SPCR = SPI_MODE;
        if( (bTmp & 0x40) != 0 )
            // if WCOL = 1
            S0SPDR;
    } while( (bTmp & 0x80) == 0 );
}

{
    __spcr_bits Tmp;
    Tmp.CPHA = 1;
    Tmp.CPOL = 1;
    Tmp.MSTR = 1;
    Tmp.LSBF = 0;
    Tmp.SPIE = 0;
    S0SPCR_bit = Tmp;
}

#define __IO_REG32_BIT(NAME, ADDRESS, ATTRIBUTE, BIT_STRUCT)\
                        volatile __no_init ATTRIBUTE union \
                         {                                 \
                           unsigned long NAME;             \
                           BIT_STRUCT NAME ## _bit;      \
                         } @ ADDRESS
__IO_REG32_BIT(S0SPSR, 0xE0020004,__READ,__spsr_bits);
//-----------------------------------
    S0SPSR = 0;
    S0SPSR;          // Warning[Pe174]: expression has no effect
    S0SPSR = 0;
//-----------------------------------
    379              S0SPSR = 0;
   \   000001BC   041082E5           STR         R1,[R2, #+0x4]
    380              S0SPSR;
    381              S0SPSR = 0;
   \   000001C0   041082E5           STR         R1,[R2, #+0x4]

//////////////////////////////////////////////////////////////////////////////
//                                                                           /
// IAR ARM ANSI C/C++ Compiler V4.41A/W32   27/Mar/2007  19:41:57 /
// Copyright 1999-2005 IAR Systems. All rights reserved.                     /
//                                                                           /
//    Cpu mode        =  arm                                                 /
//    Endian          =  little                                              /
//    Stack alignment =  4                                                   /
//    Source file     =  D:\ARM_WORK\pcmu\MAIN\SPI.C                         /
//    Command line    =  D:\ARM_WORK\pcmu\MAIN\SPI.C -D LPC2000_IAR -lC      /
//                       D:\ARM_WORK\pcmu\Works\List\ -lA                    /
//                       D:\ARM_WORK\pcmu\Works\List\ --remarks -o           /
//                       D:\ARM_WORK\pcmu\Works\Obj\ -s9 --debug --cpu_mode  /
//                       arm --endian little --cpu ARM7TDMI-S --stack_align  /
//                       4 --warnings_affect_exit_code                       /
//                       --no_path_in_file_macros -e --require_prototypes    /
//                       --fpu None --dlib_config "D:\IAR\Embedded           /
//                       Workbench\arm\LIB\dl4tpannl8n.h" -I                 /
//                       D:\ARM_WORK\pcmu\..\COMMON\RTOS\portable\IAR\LPC200 /
//                       0\ -I D:\ARM_WORK\pcmu\..\COMMON\RTOS\include\ -I   /
//                       D:\ARM_WORK\pcmu\..\COMMON\include\ -I              /
//                       D:\ARM_WORK\pcmu\MAIN\include\ -I "D:\IAR\Embedded  /
//                       Workbench\arm\INC\" --inline_threshold=2            /
//    List file       =  D:\ARM_WORK\pcmu\Works\List\SPI.s79                 /
//                                                                           /
//                                                                           /
//////////////////////////////////////////////////////////////////////////////

....

        RSEG CODE:CODE:NOROOT(2)
        CFI Block cfiBlock7 Using cfiCommon0
        CFI Function fpga_switch
        ARM
//  int fpga_switch( WORD data, WORD addr )
//  {
//  ulong value = ( 0x9C0000>>(8+2) );
//  int ret_data;
//  value |= (addr>>8)|((addr&0x1F)<<3);      
//  value <<= 8;
//  value |= (data>>8)|((data&0x1F)<<3);      
//  value <<= 2;
fpga_switch:
        LSR      R2,R1,#+8
        AND      R1,R1,#0x1F
        ORR      R1,R2,R1, LSL #+3
        ORR      R1,R1,#0x2700
        LSR      R2,R0,#+8
        AND      R0,R0,#0x1F
        ORR      R0,R2,R0, LSL #+3
        ORR      R0,R0,R1, LSL #+8
        LSL      R1,R0,#+2
//  IO0CLR = P0B_SEL_FPGA;    // Select(soft)
        MOV      R0,#-536870908
        ORR      R0,R0,#0x28000
        MOV      R2,#+268435456
        ORR      R2,R2,#0x1000
        STR      R2,[R0, #+8]
//  SSPDR  = value>>16;
        MOV      R3,#-536870904
        ORR      R3,R3,#0x68000
        LSR      R12,R1,#+16
        STR      R12,[R3, #+0]
//  IO0SET = P0B_SEL_FPGA;    // Unselect
        STR      R2,[R0, #+0]
//  while( !(SSPSR & SSPSR_RNE) );
??fpga_switch_0:
        LDR      R0,[R3, #+4]
        TST      R0,#0x4
        BEQ      ??fpga_switch_0
//  ret_data = SSPDR;
        LDR      R0,[R3, #+0]
//  SSPDR = value>>8;
        LSR      R2,R1,#+8
        STR      R2,[R3, #+0]
//  while( !(SSPSR & SSPSR_RNE) );
??fpga_switch_1:
        LDR      R2,[R3, #+4]
        TST      R2,#0x4
        BEQ      ??fpga_switch_1
//  SSPDR;
        LDR      R2,[R3, #+0]
//  SSPDR = value;
        STR      R1,[R3, #+0]
//  while( !(SSPSR & SSPSR_RNE) );
??fpga_switch_2:
        LDR      R1,[R3, #+4]
        TST      R1,#0x4
        BEQ      ??fpga_switch_2
//  SSPDR;
        LDR      R1,[R3, #+0]
//  return( ret_data );
        MOV      PC,LR           ;; return
        CFI EndBlock cfiBlock7
//  }

//  __fiq __arm void FIQ_ISR_handler(void)
//  {
FIQ_ISR_handler:
        SUB      LR,LR,#+4
        CFI ?RET R14
        PUSH     {R0-R4,LR}
        CFI ?RET Frame(CFA, -4)
        CFI R4 Frame(CFA, -8)
        CFI R3 Frame(CFA, -12)
        CFI R2 Frame(CFA, -16)
        CFI R1 Frame(CFA, -20)
        CFI R0 Frame(CFA, -24)
        CFI CFA R13+24
        SUB      SP,SP,#+16
        CFI CFA R13+40
//  ulong data;    
//  // Need for Request clear:(    
// S0SPSR;
        MOV      R8,#-536870908
        ORR      R8,R8,#0x20000
        LDR      R0,[R8, #+0]
// // Clear Interrupt
// S0SPINT = SPINT_SPIIF;
        MOV      R0,#+1
        STR      R0,[R8, #+24]
//  Read Data
//  data = S0SPDR;
        LDR      R9,[R8, #+4]
......

unsigned char SPI_ReadByte( void )
{
    S0SPDR          = 0;
    while( !(S0SPSR & 0x80) );
    return( S0SPDR );
}

void SPI_WriteByte( unsigned char bData )
{
    S0SPDR          = bData;
    while( !(S0SPSR & 0x80) );
}

    V32 dummy = S0SPSR; // dummy read of SPIF