// *** Startup Code (executed after Reset) ***
// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
        Mode_USR  EQU      0x10
        Mode_FIQ  EQU      0x11
        Mode_IRQ  EQU      0x12
        Mode_SVC  EQU      0x13
        Mode_ABT  EQU      0x17
        Mode_UND  EQU      0x1B
        Mode_SYS  EQU      0x1F
        I_Bit     EQU      0x80    /* when I bit is set, IRQ is disabled */
        F_Bit     EQU      0x40    /* when F bit is set, FIQ is disabled */
/*
// <h> Stack Configuration (Stack Sizes in Bytes)
//   <o0> Undefined Mode      <0x0-0xFFFFFFFF>
//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF>
//   <o2> Abort Mode          <0x0-0xFFFFFFFF>
//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>
//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF>
//   <o5> User/System Mode    <0x0-0xFFFFFFFF>
// </h>
*/
        UND_Stack_Size  EQU     0x00000008
        SVC_Stack_Size  EQU     0x00000100;
        ABT_Stack_Size  EQU     0x00000008
        FIQ_Stack_Size  EQU     0x00000100
        IRQ_Stack_Size  EQU     0x00000300
        USR_Stack_Size  EQU     0x00000200
AREA   STACK, DATA, READWRITE, ALIGN=2
        DS   (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
        DS   (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
        DS   (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
        DS   (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
        DS   (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
        DS   (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
Top_Stack:
// Starupt Code must be linked first at Address at which it expects to run.
AREA   STARTUPCODE, CODE, AT CODE_BASE   // READONLY, ALIGN=4
       PUBLIC  __startup
       EXTERN  CODE32 (?C?INIT)
__startup       PROC    CODE32
// Pre-defined interrupt handlers that may be directly
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (vPortYieldProcessor?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)
// Exception Vectors
// Mapped to Address 0.
// Absolute addressing mode must be used.
Vectors:        LDR     PC,Reset_Addr        
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
;                NOP                            /* Reserved Vector */
                DD      0xB9205F80
;               LDR     PC,IRQ_Addr
;                LDR     PC,[PC, #-0x0FF0]      /* Vector from VicVectAddr */
                LDR     PC,[PC, #-0x0120]      /* Vector from VicVectAddr */
                LDR     PC,FIQ_Addr
Reset_Addr:     DD      Reset_Handler
Undef_Addr:     DD      Undef_Handler?A
SWI_Addr:       DD      vPortYieldProcessor?A
PAbt_Addr:      DD      PAbt_Handler?A
DAbt_Addr:      DD      DAbt_Handler?A
                DD      0xB9205F80                      /* Reserved Address */
IRQ_Addr:       DD      IRQ_Handler?A
FIQ_Addr:       DD      FIQ_Handler?A

Reset_Handler:  
// Setup Stack for each mode
                LDR     R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
                MOV     SP, R0
                SUB     R0, R0, #SVC_Stack_Size
// Enter S Mode and set its Stack Pointer
                MSR     CPSR_c, #Mode_SYS
                MOV     SP, R0
// Start in supervisor mode
                MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
// Enter the C code
                LDR     R0,=?C?INIT
                TST     R0,#1      ; Bit-0 set: INIT is Thumb
                LDREQ   LR,=exit?A ; ARM Mode
                LDRNE   LR,=exit?T ; Thumb Mode
                BX      R0
                ENDP
PUBLIC exit?A
exit?A          PROC    CODE32
                B       exit?A
                ENDP
PUBLIC exit?T
exit?T          PROC    CODE16
exit:           B       exit?T
                ENDP
                END

      MSR     CPSR_c, #Mode_USR ; Change to User mode, Enable IRQ and FIQ
       LDR     SP, =SFE(CSTACK) & 0xFFFFFFF8    ; Initialize USR stack pointer

      /* We want to start in supervisor mode.  Operation will switch to system
      mode when the first task starts. */
     msr   CPSR_c, #Mode_SVC|I_Bit|F_Bit

    /* The last thing onto the stack is the status register, which is set for
    system mode, with interrupts enabled. */
    *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;

    #ifdef KEIL_THUMB_INTERWORK
    {        
        /* We want the task to start in thumb mode. */
        *pxTopOfStack |= portTHUMB_MODE_BIT;
    }
    #endif

//---------------------------------------------------------------------------
// Starts all the other tasks, then starts the scheduler.
//---------------------------------------------------------------------------
void main( void )
{
    // Setup the processor.
    init_cpu();
    init_delay_timer();    
    // Start Console and Console Task.
    init_console( COM_TEST_BAUD_RATE, CONSOLE_PRIORITY );
    // Hello World :-)
    boutchar( XON );
    hellomessage();
    
    xIdleTaskCreate( 200 );
extern ulong RAMEND;
extern ulong RAMSTART;
#pragma segment="HEAP_RTOS"
    bprintf( "\tRAM use:%u Heap:%8X Size:%i",
                                 (ulong)(__segment_begin( "HEAP_RTOS" ))-(ulong)&RAMSTART,
                                 __segment_begin( "HEAP_RTOS" ),
                                (ulong)&RAMEND - (ulong)(__segment_begin( "HEAP_RTOS" )) + 1 );
    if( copyprotect() )
        status_word |= STW_PROTECT;    
                    
    if( WDMOD_bit.WDTOF )
        printline( "\tWatchdog Reset Granted!");

    init_SLIC_data();
    
    init_AXE();

    vSetIdleHook( init_system );
    
    // Start the scheduler.
    vTaskStartScheduler( 0 );             // 0 - intertal timer 1 - external timer
}


//---------------------------------------------------------------------------
//
//---------------------------------------------------------------------------
void init_system()
{
    init_delay_timer();
ulong ii;
    bprintf( "\tCheck CPU -LPC%i %s", iap_getid(), (status_word & STW_PROTECT) ? "" : "Evolution" );

    boutchar( XON );
    cf_addhandler( "MAIN", main_cfg );

    bprintf(     "\tInit I2C  -%s", init_i2c() ? "Fail":"Done" );
    // Read 1st - Configuration
    bprintf_str(  "\t  Config  -" );
    ii = cf_parser( FALSE );
    if( ii )
        bprintf( ii == 1 ? "Empty" : "Failed" );
    else
        bprintf(  "Ok" );
    
    if( config_flags & DEVICE_OWIRE )
      {    print_str(  "\tCheck OW  -" );
        init_ow();
    }
    bprintf(     "\tInit SPI0 -%s", init_SPI0() ? "Fail":"Done" );
    bprintf(     "\tInit CPLD -%s", init_cpld()    ? "Fail":"Ok" );
    
    bprintf(     "\tInit SPI1 -%s", init_SPI1() ? "Fail":"Done" );
    
    bprintf_str( "\tLoad FPGA -" ); load_fpga( 0x20000, TRUE );

    bprintf(     "\tInit ACSL -%s", init_armsl() ? "Fail":"Ok" );

    init_dsl_post();

    init_eth_post();

    toggle_red_LED();

    // Check Maintenance Console Request
    for( ii=0; ii< 50; ii++ )
    {   if( IO0PIN_bit.P0_14 == 0 )
        {    status_word |= STW_MAINTENANCE;
            bprintf( "\nMaintenance Console Mode" );
            goto skip_application;
        }
               vDummyDelay_ms( 2 );
    }
    //----- Switch System to external 2ms Ticks -----------------------------
    bprintf_str( "\tExt Sync  -" );
    ENTER_CRITICAL();
    {
    // Set edle-sensetive Mode
    // Bug :-(
    // The steps involved in the configuration of the EXTMODE and/or EXTPOLAR would be as follow:-
    // 1. Write 0x00 to VPBDIV
    // 2. Write the desired value to EXTMODE or EXTPOLAR register
    // 3. Write the same value to VPBDIV
    // 3a. Write 0x00 to VPBDIV (additional step for INT0 )
    // 4. Restore the VPBDIV to the previously saved value or simply write to the register again
    //    with the desired value.
    VPBDIV = 0;                 // 1.
    ii = EXTMODE & ( EXTMODE_EXTMODE0|EXTMODE_EXTMODE1|EXTMODE_EXTMODE2|EXTMODE_EXTMODE3);  // Get Curent Value
    ii |= EXTMODE_EXTMODE1;
    EXTMODE = ii;             // 2.
    VPBDIV  = ii;             // 3.
    VPBDIV  = 0;              // 3a
    VPBDIV  = configBUS_CLK; // 4.

    // Select IRQ Pin 'IRQ_2MS'
    PINSEL0_bit.P_IRQ_2MS = 0x2;            // Pin to EINT1 mode

    // IRQ Handler to Temporary MS2_ISR_handler()
    VICIntSelect &= ~(1 << VIC_EINT1);         // Classifies as IRQ.
      VICVectAddr9 = (ulong)MS2_ISR_handler;     // Connect to Slot9
      VICVectCntl9 = 0x20 | VIC_EINT1;          // Enable vector interrupt for EINT1.
    VICIntEnable =  (1 << VIC_EINT1);       // Enable EINT1 2ms interrupt.

    }

    LEAVE_CRITICAL();

    // Enable 2ms in FPGA
    work_spi_reset_clr( CSPI_WR | CSPI_RES_FPGA );
    ms_check_timer = 0;
    vDummyDelay_ms( (16+1)*2 );
    if( ms_check_timer >= 16 )
    {    // Ok 2ms Present.
        ENTER_CRITICAL();
        {
        // Disable INT Generate timer 0 compare match.
        TxMCR &= (~0x01);
        // Set New Handler
//        VICIntSelect &= ~(1 << VIC_EINT1);         // Classifies as IRQ.
          VICVectAddr0 = (ulong)vPortPreemptiveTickEntry_Ext;;     // Connect to Slot9
          VICVectCntl0 = 0x20 | VIC_EINT1;          // Enable vector interrupt for EINT1.
//        VICIntEnable =  (1 << VIC_EINT1);       // Enable EINT1 2ms interrupt.
        }
        LEAVE_CRITICAL();
        bprintf( "Ok (%i)", ms_check_timer );
        // For future....
//!!        sys_reg |= (SYS_2MS_IRQ | SYS_PKT_ENABLE);
    }
    else
    {    // 2ms Failed
          VICIntEnClear = (1<< VIC_EINT1);          // Disable vector interrupt for EINT1.
        work_spi_reset( CSPI_WR | CSPI_RES_FPGA );
        bprintf( "Failed (%i)", ms_check_timer );
        goto skip_application;
    }


    //-----------------------------------------------------------------------
    
    bprintf(     "\tInit SWH  -%s", init_switch() ? "Fail":"Done" );

    printline( "Ready" );

    sys_pkt( sys_reg );


skip_application:
    xTaskCreate( CheckerProcess, "Checker", configMINIMAL_STACK_SIZE*2, NULL, CHECK_TASK_PRIORITY, NULL );

    vSetIdleHook( idle_system );
    off_red_LED();
}

#if UIP_FIXEDADDR > 0
const u16_t uip_hostaddr[2] =
  {HTONS((UIP_IPADDR0 << 8) | UIP_IPADDR1),
   HTONS((UIP_IPADDR2 << 8) | UIP_IPADDR3)};
const u16_t uip_arp_draddr[2] =
  {HTONS((UIP_DRIPADDR0 << 8) | UIP_DRIPADDR1),
   HTONS((UIP_DRIPADDR2 << 8) | UIP_DRIPADDR3)};
const u16_t uip_arp_netmask[2] =
  {HTONS((UIP_NETMASK0 << 8) | UIP_NETMASK1),
   HTONS((UIP_NETMASK2 << 8) | UIP_NETMASK3)};
#else
u16_t uip_hostaddr[2];      
u16_t uip_arp_draddr[2], uip_arp_netmask[2];
#endif /* UIP_FIXEDADDR */

...
/**
* \internal Internal variables that are set using the macros
* uip_setdraddr and uip_setnetmask.
*/
extern u16_t uip_arp_draddr[2], uip_arp_netmask[2];
//u16_t uip_arp_draddr[2], uip_arp_netmask[2];
#endif /* __UIP_ARP_H__ */

STMDB     R13!,{R4,R14}

#ifdef REALVIEW_ARM7
    #include "../../Source/portable/RealView/ARM7/portmacro.h"
#endif

SUBS    PC, LR, #4