Freescale’s e200z6 Core
High-performance 132 MHz 32-bit PowerPC Book E-compliant core
Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory
2 MB of embedded Flash memory with Error Correction Coding (ECC) and Read While Write capability (RWW)
64 KB on-chip static RAM with Error Correction Coding (ECC)
32 KB of cache (with line-locking) that can be configured as additional RAM

System
Two enhanced time processor units (eTPUs) with 64 I/O channels and 19k of designated SRAM
64-channel eDMA (Enhanced Direct Memory Access) controller
Interrupt controller (INTC) capable of handling 286 selectable-priority interrupt sources
Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
MPC500 compatible External Bus Interface
Nexus IEEE-ISTO 5001™ Class 3+ multicore debug capabilities
5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
416 pin PBGA package
Temperature Range: -40 to 125?C
Optional Temperature Range: -55 to 125?C

I/O
40 channel dual Enhanced queued analog-to-digital converter (eQADC) - up to 12 bit resolution and up to 1.25ms conversions, 6 queues with triggering and DMA support
Four deserial serial peripheral
Interface (DSPI) modules - 16 bits wide up to 6 chip selects each
Three controller area
Network (CAN) modules with 64 buffers each
Two enhanced serial communication
Interface (eSCI) modules
24 channel enhanced multiple I/O system (EMIOS) with unified channels