#define F_CPU 12500000UL  // 12.5 MHz

int main(void){

        /***init SPI as USART MSPIM and ~SS line ***/
        //Calculation of BRREG value. USART MSPIM:
        #define BPS 10000                                 //Desired bit rate for SPI communication.
        #define BRREG ((F_CPU/(2*BPS))-1)       // Calculated brreg value.
                                                                    //SPI clock t1: max = 4*tclock_ads1256 = 2 MHz
        init_usart_spi(0, BRREG);

        /***enable interrupt***/
        sei();

        /***enable ADS1256***/
        init_ads1256();

        while(1){.....}
}

** Инициализация ads1256

void init_ads1256(void){

        //***Initialise ADS1256
        char Byte=(WREG | 0x00);                //Starting at address 0x00,
        queue_byte(Byte);
        queue_byte(0x04);                       //write to a total of 5 registers (5 - 1 = 0x04)
        queue_byte(0x06);                       //STATUS register = 0x06
        queue_byte(0x01);                       //MUX register = 0x01
        queue_byte(0x01);                       //ADCON register = 0x01
        queue_byte(0xC1);                       //DRATE register = 0xC1
        queue_byte(0x00);                       //GPIO register = 0x00
        //ADS1256 Self Calibration
        queue_byte(SELFCAL);                    //Initiate self calibration
        _delay_ms(10);
//      do{char temp   =   PD3;} while((temp & 0x08) == 0x08);       //Wait for DRDY to go low
        //Set sample freq. to 500SPS

        //***Initialise External interrupt 1
        //PORTD3 is input by default
        //The low level of INT1 generates an interrupt request
        cbi(EICRA, ISC11);
        cbi(EICRA, ISC10);
        //enable INT1 interrupt
        sbi(EIMSK, INT1);

}


** Действия когда DRDY становится низким

//The following function will be called when analog conversion is done: DRDY connecting to PD3/INT1 is going low
ISR(INT1_vect) {

        //spi_send_mssp(_ADS1256_cmd_read_regs | _ADS1256_regs_io)
        queue_byte(RDATA);
        //spi_send_mssp(0)
        queue_byte(0);
        _delay_us(10);                 //*ADS1256 t6 VERY IMPORTANT* min_us=t6/F_ADS1256=50/7.68MHz=7us
        //spi_read_mssp(data)
        DAT[conv]=fetch_byte();
        DAT[conv+1]=fetch_byte();
        DAT[conv+2]=fetch_byte();
        conv=conv+3;
        //clear INT1 interrupt flag
        sbi(EIFR, INTF1);
}

/* Calculation of BRREG value. */
#define CPUFREQ 12500000UL
#define BPS 10000 //!< Desired bit rate for SPI communication.
#define brreg ((CPUFREQ/(2*BPS))-1) //!< Calculated brreg value.
/* USART line definitions. */
#define USARTDDR DDRD //!< The data direction register for the USART lines.
#define XCKPIN PD4 //!< The bit position for the USART XCK line.

uint8_t spimode=0;


        // Baud rate must be set to 0 prior to enabling the USART as SPI
        // master, to ensure proper initialization of the XCK line.
        UBRR0 = 0;

        // Set XCK line to output, ie. set USART in master mode.
        USARTDDR |= (1<<XCKPIN);

        // Set USART to Master SPI mode.
        UCSR0C = (1<<UMSEL01) | (1<<UMSEL00);

        // Set clock polarity and phase to correct SPI mode.
        if( spimode & 0x01 ) UCSR0C |= (1<<UCPOL0);
        if( spimode & 0x02 ) UCSR0C |= (1<<UCPHA0);

        // Enable RX and TX.
        UCSR0B = (1<<RXEN0) | (1<<TXEN0);

        // Set baud rate. Must be set _after_ enabling the transmitter.
        UBRR0 = brreg;

        // Wait for empty transmit buffer.
        do {} while( (UCSR0A & (1<<UDRE0)) == 0 );
        Byte=(RREG | 0x00);                //прочитать регистры начиная с 0x00
        UDR0 =  Byte;
        // Wait for transfer to complete
        do {} while( (UCSR0A & (1<<RXC0)) == 0 );
        UDR0 =  0x03;                        //прочитать 4 регистра
        // Wait for transfer to complete
        do {} while( (UCSR0A & (1<<RXC0)) == 0 );
        delay_us(10);                         //Задержка перед чтением
        a0=UDR0;
        a1=UDR0;
        a2=UDR0;
        a3=UDR0;

     a0 a1 a2 a3

1n  90 78 90 90
2n  70 ff 70 70
3n  00 00 00 00
4n  18 00 18 18