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# Define Device, Package And Speed Grade
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CONFIG PART = xc5vfx30t-ff665-1;

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# User Time Names / User Time Groups / Time Specs
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# CONFIG STEPPING = "ES";

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# User Physical Constraints
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# Pinout and Related I/O Constraints
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#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#

NET "sys_reset_n"      LOC = "H9"  | IOSTANDARD = LVCMOS33 | PULLUP | NODELAY;

#
# SYS clock 250 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-5 GTX
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GTX Transceiver Tile.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-5 GTX Transceiver User Guide
# (UG198) for guidelines regarding clock resource selection.
#

NET  "sys_clk_p"       LOC = "T4";
NET  "sys_clk_n"       LOC = "T3";
INST "refclk_ibuf"     DIFF_TERM = "TRUE";

#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-5 GTX Transceiver User Guide (UG198) for more
# information.
#
# PCIe Lanes 0
INST "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X0Y1;

#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#

INST "ep/pcie_ep0/pcie_blk/pcie_ep"                       LOC = PCIE_X0Y0;

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# Physical Constraints
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#
# BlockRAM placement
#

INST "ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"      LOC = RAMB36_X4Y4;
INST "ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X4Y3;
INST "ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X4Y2;
INST "ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X4Y1;
INST "ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X4Y0;


###############################################################################
# Timing Constraints
###############################################################################

#
# Ignore timing on asynchronous signals.
#

NET "sys_reset_n" TIG;

#
# Timing requirements and related constraints.
#

NET "sys_clk_c"                                      PERIOD = 10ns;

NET "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out" TNM_NET = "MGTCLK";

TIMESPEC "TS_MGTCLK"  = PERIOD "MGTCLK" 100.00 MHz HIGH 50 %;

# LEDs

NET "led1"  LOC = "E10"  | IOSTANDARD = LVTTL;
NET "led2"  LOC = "F10"  | IOSTANDARD = LVTTL;
NET "led3"  LOC = "F20"  | IOSTANDARD = LVTTL;
NET "led4"  LOC = "G21"  | IOSTANDARD = LVTTL;

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# End
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