signal cnt : std_logic_vector(7 downto 0);

cnt : process (clk80)
begin
   if (clk80=1 and clk80'event) then
       cnt <= cnt+1;
   end if;
end process;

out1 <= cnt(0);
out2 <= cnt(1);
out3 <= cnt(2);
...
out8 <= cnt(7);

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    17:55:55 05/04/2008
-- Design Name:
-- Module Name:    counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( IN80 : in  STD_LOGIC;
           IN100 : in  STD_LOGIC;
           OUT1 : out  STD_LOGIC;
           OUT2 : out  STD_LOGIC;
           OUT3 : out  STD_LOGIC;
           OUT4 : out  STD_LOGIC;
           OUT5 : out  STD_LOGIC;
           OUT6 : out  STD_LOGIC;
           OUT7 : out  STD_LOGIC;
           OUT8 : out  STD_LOGIC);
end counter;

architecture Behavioral of counter is

signal cnt : std_logic_vector(7 downto 0);

cnt : process (clk80)
begin
   if (clk80=1 and clk80'event) then
       cnt <= cnt+1;
   end if;
end process;

out1 <= cnt(0);
out2 <= cnt(1);
out3 <= cnt(2);
out4 <= cnt(3);
out5 <= cnt(4);
out6 <= cnt(5);
out7 <= cnt(6);
out8 <= cnt(7);
end Behavioral;

process (IN80 )
begin
   if (IN80'event and IN80 ='1') then
       cnt <= cnt+'1';
   end if;
end process;

entity counter is
    Port ( IN80 : in  STD_LOGIC;
           IN100 : in STD_LOGIC;
           OUT1 : out STD_LOGIC;
           OUT2 : out STD_LOGIC;
           OUT3 : out STD_LOGIC;
           OUT4 : out STD_LOGIC;
           OUT5 : out STD_LOGIC;
           OUT6 : out STD_LOGIC;
           OUT7 : out STD_LOGIC;
           OUT8 : out STD_LOGIC);
end counter;

architecture Behavioral of counter is

signal counter : std_logic_vector(7 downto 0);

begin

process (IN80 )
begin
if (IN80 ='1' and IN80 'event) then
counter <= counter+'1';
end if;
end process;
    
out1 <= counter(0);
out2 <= counter(1);
out3 <= counter(2);
out4 <= counter(3);
out5 <= counter(4);
out6 <= counter(5);
out7 <= counter(6);
out8 <= counter(7);
end Behavioral;

  

module DSS(input clk, input [6:0] freq, output f_out);

reg [7:0] cnt = 8'b0;

always @(posedge clk)

cnt <= cnt + {1'b0,freq};

assign f_out = cnt[7];

endmodule