Код
entity main is
Port ( clk : in STD_LOGIC;
cl1 : out STD_LOGIC;
cl2 : out STD_LOGIC;
flm : out STD_LOGIC;
d0 : out STD_LOGIC;
d1 : out STD_LOGIC;
d2 : out STD_LOGIC;
d3 : out STD_LOGIC);
end main;
architecture Behavioral of main is
begin
main : process(clk)
variable x_counter : integer :=0;
variable flm_counter : integer :=0;
variable cl2_counter : integer :=0;
variable cl1_counter : integer :=0;
variable clk_counter : integer :=0;
variable cl2_val : std_logic :='0';
variable cl1_val : std_logic :='0';
begin
if (clk='1') then
clk_counter := clk_counter + 1;
if (clk_counter = 1) then --cl2 rise
cl2_val := not cl2_val;
cl2 <= cl2_val;
if (cl2_val='1') then --data
d0 <= '0';
d1 <= '0';
d2 <= '1';
d3 <= '0';
cl2_counter := cl2_counter + 1;
end if;
elsif ((clk_counter = 2) AND (cl2_val = '1')) then --cl1
cl1_val := not cl1_val;
cl1 <= cl1_val;
elsif (clk_counter = 5) then --cl2 fall
--cl2_val := '0';
--cl2 <= cl2_val;
clk_counter := 0;
end if;
end if;
end process main;
end Behavioral;
Port ( clk : in STD_LOGIC;
cl1 : out STD_LOGIC;
cl2 : out STD_LOGIC;
flm : out STD_LOGIC;
d0 : out STD_LOGIC;
d1 : out STD_LOGIC;
d2 : out STD_LOGIC;
d3 : out STD_LOGIC);
end main;
architecture Behavioral of main is
begin
main : process(clk)
variable x_counter : integer :=0;
variable flm_counter : integer :=0;
variable cl2_counter : integer :=0;
variable cl1_counter : integer :=0;
variable clk_counter : integer :=0;
variable cl2_val : std_logic :='0';
variable cl1_val : std_logic :='0';
begin
if (clk='1') then
clk_counter := clk_counter + 1;
if (clk_counter = 1) then --cl2 rise
cl2_val := not cl2_val;
cl2 <= cl2_val;
if (cl2_val='1') then --data
d0 <= '0';
d1 <= '0';
d2 <= '1';
d3 <= '0';
cl2_counter := cl2_counter + 1;
end if;
elsif ((clk_counter = 2) AND (cl2_val = '1')) then --cl1
cl1_val := not cl1_val;
cl1 <= cl1_val;
elsif (clk_counter = 5) then --cl2 fall
--cl2_val := '0';
--cl2 <= cl2_val;
clk_counter := 0;
end if;
end if;
end process main;
end Behavioral;
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