Посмотрите плз. код.
Хотелось бы сделать так как показыно на картинке ну и с наименьшими затратами ресурсов в FPGA.
Сигнал DRY не зависел от длинны ND.
Ну и передний фрот DRY на 180 сдвинут от CLK.
Спасибо.
Код
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity a2b is
port(
CLK: in std_logic;
RSTl: in std_logic;
ND: in std_logic;
DIN: in std_logic_vector(15 downto 0);
DRY: out std_logic;
DOUT: out std_logic_vector(15 downto 0)
);
end a2b;
architecture a2b_arch of a2b is
signal DRY1: std_logic;
signal R: std_logic;
begin
P1: process (CLK, RSTl)
begin
if RSTl = '0' then
DRY1 <= '0';
DOUT <= (others => '0');
elsif CLK'event and CLK = '1' then
if ND = '1' then
DOUT <= DIN;
DRY1 <= '1';
else
DRY1 <= '0';
end if;
end if;
end process P1;
P2: process (CLK, RSTl, R)
begin
if RSTl = '0' then
DRY <= '0';
R <= '0';
elsif CLK'event and CLK = '0' then
if R = '1' then
DRY <= '0';
elsif DRY1 = '1' then
DRY <= '1';
R <= '1';
else
R <= '0';
end if;
end if;
end process P2;
end a2b_arch;
Нажмите для просмотра прикрепленного файла
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity a2b is
port(
CLK: in std_logic;
RSTl: in std_logic;
ND: in std_logic;
DIN: in std_logic_vector(15 downto 0);
DRY: out std_logic;
DOUT: out std_logic_vector(15 downto 0)
);
end a2b;
architecture a2b_arch of a2b is
signal DRY1: std_logic;
signal R: std_logic;
begin
P1: process (CLK, RSTl)
begin
if RSTl = '0' then
DRY1 <= '0';
DOUT <= (others => '0');
elsif CLK'event and CLK = '1' then
if ND = '1' then
DOUT <= DIN;
DRY1 <= '1';
else
DRY1 <= '0';
end if;
end if;
end process P1;
P2: process (CLK, RSTl, R)
begin
if RSTl = '0' then
DRY <= '0';
R <= '0';
elsif CLK'event and CLK = '0' then
if R = '1' then
DRY <= '0';
elsif DRY1 = '1' then
DRY <= '1';
R <= '1';
else
R <= '0';
end if;
end if;
end process P2;
end a2b_arch;
