LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.all;

ENTITY mem IS
    PORT
    (
        clock        : IN STD_LOGIC;
        data        : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
        rdaddress        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        wraddress        : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
        wren        : IN STD_LOGIC  := '1';
        q        : OUT STD_LOGIC_VECTOR (14 DOWNTO 0)
    );
END mem;


ARCHITECTURE SYN OF mem IS

    SIGNAL sub_wire0    : STD_LOGIC_VECTOR (14 DOWNTO 0);



    COMPONENT altsyncram
    GENERIC (
        address_reg_b        : STRING;
        clock_enable_input_a        : STRING;
        clock_enable_input_b        : STRING;
        clock_enable_output_a        : STRING;
        clock_enable_output_b        : STRING;
        intended_device_family        : STRING;
        lpm_type        : STRING;
        numwords_a        : NATURAL;
        numwords_b        : NATURAL;
        operation_mode        : STRING;
        outdata_aclr_b        : STRING;
        outdata_reg_b        : STRING;
        power_up_uninitialized        : STRING;
        ram_block_type        : STRING;
        read_during_write_mode_mixed_ports        : STRING;
        widthad_a        : NATURAL;
        widthad_b        : NATURAL;
        width_a        : NATURAL;
        width_b        : NATURAL;
        width_byteena_a        : NATURAL
    );
    PORT (
            wren_a    : IN STD_LOGIC;
            clock0    : IN STD_LOGIC;
            address_a    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
            address_b    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
            q_b    : OUT STD_LOGIC_VECTOR (14 DOWNTO 0);
            data_a    : IN STD_LOGIC_VECTOR (14 DOWNTO 0)
    );
    END COMPONENT;

BEGIN
    q    <= sub_wire0(14 DOWNTO 0);

    altsyncram_component : altsyncram
    GENERIC MAP (
        address_reg_b => "CLOCK0",
        clock_enable_input_a => "BYPASS",
        clock_enable_input_b => "BYPASS",
        clock_enable_output_a => "BYPASS",
        clock_enable_output_b => "BYPASS",
        intended_device_family => "Cyclone II",
        lpm_type => "altsyncram",
        numwords_a => 256,
        numwords_b => 256,
        operation_mode => "DUAL_PORT",
        outdata_aclr_b => "NONE",
        outdata_reg_b => "CLOCK0",
        power_up_uninitialized => "FALSE",
        ram_block_type => "M4K",
        read_during_write_mode_mixed_ports => "DONT_CARE",
        widthad_a => 8,
        widthad_b => 8,
        width_a => 15,
        width_b => 15,
        width_byteena_a => 1
    )
    PORT MAP (
        wren_a => wren,
        clock0 => clock,
        address_a => wraddress,
        address_b => rdaddress,
        data_a => data,
        q_b => sub_wire0
    );



END SYN;

mem_inst : mem PORT MAP (
        clock     => clock_sig,
        data     => data_sig,
        rdaddress     => rdaddress_sig,
        wraddress     => wraddress_sig,
        wren     => wren_sig,
        q     => q_sig
    );