_DINT(); // disable interrupts

   // 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected.
   PLL0CON_bit.PLLC = 0;
   PLL0FEED = 0xAA;
   PLL0FEED = 0x55;

   // 2. Disable PLL0 with one feed sequence.
   PLL0CON_bit.PLLE = 0;
   PLL0FEED = 0xAA;
   PLL0FEED = 0x55;

   // 3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired.
   CCLKCFG_bit.CCLKSEL = 3;

   // 4. Write to the Clock Source Selection Control register to change the clock source if
   //    needed.
   CLKSRCSEL_bit.CLKSRC = 2; // RTC is PLL clock source.

   // 5. Write to the PLL0CFG and make it effective with one feed sequence. The PLL0CFG
   //    can only be updated when PLL0 is disabled.
   PLL0CFG_bit.MSEL = 13733 - 1;  // 30.0002 MHz
   PLL0CFG_bit.NSEL = 3 - 1;
   PLL0FEED = 0xAA;
   PLL0FEED = 0x55;

   // 6. Enable PLL0 with one feed sequence.
   PLL0CON_bit.PLLE = 1;
   PLL0FEED = 0xAA;
   PLL0FEED = 0x55;

   // 7. Change the CPU Clock Divider setting for the operation with PLL0. It is critical to do
   //    this before connecting PLL0.
   CCLKCFG = 10-1;   // divide by 10
   PCLKSEL0 = PCLKSEL1 = 0;

   // 8. Wait for the PLL to achieve lock, 200 / FREF seconds when FREF is less than 400 kHz
   GlobalTimeStart();
   DelayMs( 200000UL/32768UL );

   // 9. Connect PLL0 with one feed sequence.
   PLL0CON_bit.PLLC = 1;
   PLL0FEED = 0xAA;
   PLL0FEED = 0x55;