mrs r0, cpsr
  bic r0, r0, #0x1F
  orr r1, r0, #0x13
  msr cpsr_cxsf, r1

static long ram_size(ulong *base, long maxsize)
{
    volatile long    *test_addr;
    volatile ulong    *base_addr = base;
    ulong        ofs;        /* byte offset from base_addr */
    ulong        save;        /* to make test non-destructive */
    ulong        save2;        /* to make test non-destructive */
    long        ramsize = -1;    /* size not determined yet */

    save = *base_addr;        /* save value at 0 so can restore */
    save2 = *(base_addr+1);    /* save value at 4 so can restore */

    /* is any SRAM present? */
    *base_addr = 0x5555aaaa;

    /* It is important to drive the data bus with different data so
     * it doesn't remember the value and look like RAM that isn't there.
     */
    *(base_addr + 1) = 0xaaaa5555;    /* use write to modify data bus */

    if (*base_addr != 0x5555aaaa)
    ramsize = 0;        /* no RAM present, or defective */
    else {
    *base_addr = 0xaaaa5555;
    *(base_addr + 1) = 0x5555aaaa;    /* use write to modify data bus */
    if (*base_addr != 0xaaaa5555)
        ramsize = 0;    /* no RAM present, or defective */
    }

    /* now size it if any is present */
    for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
    test_addr = (long*)((long)base_addr + ofs);    /* location to test */

    *base_addr = ~*test_addr;
    if (*base_addr == *test_addr)
        ramsize = ofs;    /* wrapped back to 0, so this is the size */
    }

    *base_addr = save;        /* restore value at 0 */
    *(base_addr+1) = save2;    /* restore value at 4 */
    return (ramsize);
}

{
    V8 *p = 0x00;
    HANDLE h;

    GetExceptionVector( EXPVECT_DABT,  &h);
    SetExceptionVector( EXPVECT_DABT,  DabtDetHandler);

    while ( !DabtHappened )
    {
         p += 1*M;
         *p;
    }

    SetExceptionVector( EXPVECT_DABT, h);
    return (U32)p - 1;
}

;
; Disable L2 cache
;
ldr r1, =CSP_BASE_REG_PA_L2CC
ldr r0, =0x0
str r0, [r1, #L2CC_CR_OFFSET]