при использовании chipscope, подключаю в нужном модуле ila с icon
Код
/*===============================================================================
=================*/
wire [63:0] trig_ila_64;
wire [35:0] control0;
/*===============================================================================
=================*/
assign trig_ila_64[63:0] = ...;
ila_64 ila64 (.CLK(pix_clk), .TRIG0 (trig_ila_64), .CONTROL (control0)) /* synthesis syn_noprune =1 */;
icon_0 icon0 (.CONTROL0 (control0)) /* synthesis syn_noprune =1 */;
=================*/
wire [63:0] trig_ila_64;
wire [35:0] control0;
/*===============================================================================
=================*/
assign trig_ila_64[63:0] = ...;
ila_64 ila64 (.CLK(pix_clk), .TRIG0 (trig_ila_64), .CONTROL (control0)) /* synthesis syn_noprune =1 */;
icon_0 icon0 (.CONTROL0 (control0)) /* synthesis syn_noprune =1 */;
где pix_clk - глобальный
и при имплементе выходят такие варнинги
Route:455 - CLK Net:u_rgb2ycrcb/control0[13] may have excessive skew because
1 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
PhysDesignRules:372 - Gated clock. Clock net u_rgb2ycrcb/control0[13] is
sourced by a combinatorial pin. This is not good design practice. Use the CE
pin to control the loading of data into the flip-flop.
при использовании identify, уже на этапе синтеза вылетает со следующей ошибкой
BN245 Port 'pix_clk' on Chip 'vout_m' drives 1 PAD loads and 84 non PAD loads
где может быть зарыто? тыкните пожайлуста
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