Код
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ip_header is
generic
(
C_IP_ADDR_DST : std_logic_vector := X"ac1e69bf"
);
port
(
RFF_WR_CLK_IN : in std_logic;
RFF_DATA_IN : in std_logic_vector(0 to 31);
RFF_WR_REQ_IN : in std_logic;
RFF_DATA_OUT : out std_logic_vector(0 to 31);
RFF_WR_REQ_OUT : out std_logic
-- RFF_FULL_OUT : out std_logic
);
end entity ip_header;
architecture IMP of ip_header is
signal remove34_cnt : std_logic_vector(0 to 34) := "000" & X"00000000";
signal ip_addr_dst : std_logic_vector(0 to 31) := X"00000000";
signal ip_src_wrong : std_logic := '0';
signal write_cnt : std_logic_vector(0 to 1) := "00";
begin
RFF_DATA_OUT <= X"000008" & RFF_DATA_IN(24 to 31) when ( write_cnt(0) and RFF_WR_REQ_IN ) = '1' else
X"000000" & RFF_DATA_IN(24 to 31) when ( write_cnt(1) and RFF_WR_REQ_IN ) = '1' else
X"00000000";
RFF_WR_REQ_OUT <= ( write_cnt(0) or write_cnt(1) ) and RFF_WR_REQ_IN;
process( RFF_WR_CLK_IN )
begin
if ( RFF_WR_CLK_IN='1' and RFF_WR_CLK_IN'event ) then
if ( RFF_DATA_IN(20)='1' and RFF_WR_REQ_IN='1' ) then
remove34_cnt <= "100" & X"00000000";
elsif ( RFF_DATA_IN(20)/='1' and RFF_WR_REQ_IN='1' ) then
remove34_cnt <= '0' & remove34_cnt(0 to 33);
end if;
if ( remove34_cnt(25)='1' or remove34_cnt(26)='1' or remove34_cnt(27)='1' or remove34_cnt(28)='1' ) then
ip_addr_dst <= ip_addr_dst(8 to 31) & ip_addr_dst(0 to 7);
elsif ( ( remove34_cnt(25) or remove34_cnt(26) or remove34_cnt(27) or remove34_cnt(28) ) = '1' and ( ip_addr_dst(0 to 7) /= RFF_DATA_IN(24 to 31) ) ) then
ip_src_wrong <= '1';
elsif ( remove34_cnt(24)='1' ) then
ip_addr_dst <= C_IP_ADDR_DST;
ip_src_wrong <= '0';
end if;
if ( ip_src_wrong='0' and remove34_cnt(32)='1' ) then
write_cnt <= "10";
elsif ( ip_src_wrong='0' and remove34_cnt(33)='1' ) then
write_cnt <= "01";
elsif ( RFF_DATA_IN(20)='1' ) then
write_cnt <= "00";
else
write_cnt <= "00";
end if;
end if;
end process;
end IMP;