-----------------

--! Standard libraries
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


--! Entity
entity a_mult is
generic(
ARITH_DATA_A_MSB : integer; --! Data input A bus MSB
ARITH_DATA_B_MSB : integer; --! Data input B bus MSB
RESULT_DATA_MSB : integer --! Result data bus MSB
);
port(
-- Main
rst : in std_logic; --! Asynchronous reset
clk : in std_logic; --! Clock
-- Memory
a : in std_logic_vector(ARITH_DATA_A_MSB downto 0); --! Arithmetic port a write data
b : in std_logic_vector(ARITH_DATA_B_MSB downto 0); --! Arithmetic port b write data
p : out std_logic_vector(RESULT_DATA_MSB downto 0) --! Arithmetic result read data
);
end a_mult;

--! Architecture
architecture rtl of a_mult is

-- Width of the intermediate result value
constant RESULT_WIDTH : natural := get_min((RESULT_DATA_MSB+1),(ARITH_DATA_A_MSB+1+ARITH_DATA_B_MSB+1));

signal a_p2 : signed(ARITH_DATA_A_MSB downto 0);
signal b_p2 : signed(ARITH_DATA_B_MSB downto 0);
signal p1 : signed(ARITH_DATA_A_MSB+1+ARITH_DATA_B_MSB downto 0);

begin

-- Connect result data to output ports
-- * Drop rightmost bits if RESULT_DATA_MSB is smaller than ARITH_DATA_A_MSB+1+ARITH_DATA_B_MSB
-- * Fill left side with sign bit if RESULT_DATA_MSB is bigger than ARITH_DATA_A_MSB+1+ARITH_DATA_B_MSB
p <= std_logic_vector(resize(p1(ARITH_DATA_A_MSB+1+ARITH_DATA_B_MSB downto (ARITH_DATA_A_MSB+1+ARITH_DATA_B_MSB)-(RESULT_WIDTH-1)), RESULT_DATA_MSB+1));

p_seq : process(rst, clk)
begin
if ( rst = '1') then

a_p2 <= (others => '0');
b_p2 <= (others => '0');

p1 <= (others => '0');

elsif (rising_edge(clk)) then

-- Capture input data to pipeline registers
a_p2 <= signed(a);
b_p2 <= signed(;

-- Multiply registered values
p1 <= a_p2 * b_p2;

end if;
end process p_seq;

end rtl;

---------------

`ifdef __USE_ALTERA_MACRO__
      lpm_mult
      #(
        .lpm_hint           ( "INPUT_B_IS_CONSTANT=NO,DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5" ) ,
        .lpm_widtha         ( pIDAT_W                                                                      ) ,
        .lpm_widthb         ( pDAT2COE_W                                                                   ) ,
        .lpm_widthp         ( cMULT_W                                                                      ) ,
        .lpm_widths         ( 1                                                                            ) ,
        .lpm_type           ( "LPM_MULT"                                                                   ) ,
        .lpm_representation ( "SIGNED"                                                                     ) ,
        .lpm_pipeline       ( 2                                                                            )        // do as parameter
      )
      lpm_mult
      (
        .dataa  ( oerr        ),
        .datab  ( dat2coe [i] ),
        .clken  ( iclkena     ),
        .clock  ( iclk        ),
        .result ( mult    [i] ),
        .aclr   ( 1'b0        ),
        .sum    ( 1'b0        )
      );
`endif

--------------------------------------------------------------------------------
-- You must compile the wrapper file mult_36x32.vhd when simulating
-- the core, mult_36x32. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY mult_36x32 IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(67 DOWNTO 0)
);
END mult_36x32;

ARCHITECTURE mult_36x32_a OF mult_36x32 IS
-- synthesis translate_off
COMPONENT wrapped_mult_36x32
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(67 DOWNTO 0)
);
END COMPONENT;

-- Configuration specification
FOR ALL : wrapped_mult_36x32 USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 36,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 32,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 4,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 67,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mult_36x32
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on

END mult_36x32_a;