Пользователь AVR по теме могу подсказать, напишите пожалуйста мне на почту.

Было дело давно Но посмотрел, Nios не использовал, дабы не было время разбираться. Правильно понимаете что без MAC. В качестве MAC я использовало корку с OPENCORE сайта, работает нормально. Вот в принципе и все. Т.е. подавал данные с MAC уровня, ряелизованного на логике и разбирал там же. Моя проблема использования всех этих вещей была в том, что короткое время подавал RESET на Marvel 88E1111 (надо дольше было) и далее перед его дальнейшей конфигурацией надо выждать довольно большое время (по мануалу) я не ждал. Вот в принципе и все проблемы.

// Cyclone IV GX FPGA Dev Kit Board Update Portal Top-Level
// c4gx15_starter_bup.v - v9.1.1

module c4gx15_starter_bup // revA board
(
input clkin_sys, // input to osc_clk 50Mhz
input clkin_enet, // sent to tx_clk_to_the_tse_mac 125Mhz

output [23:0] fsml_a,
inout [15:0] fsml_d,
output fsml_oen,
output fsml_wen,
output flash_cen,
output [1:0] ssram_bwn,
output ssram_clk,
output ssram_cen,
output max2_csn,
output lcd_csn,

input [1:0] user_pb,
output [3:0] user_led,

output enet_mdc,
inout enet_mdio,
input enet_intn,
input enet_rx,
output enet_tx,
output enet_resetn,

input cpu_resetn
);

wire mdio_in_to_the_tse_mac;
wire mdio_oen_from_the_tse_mac;
wire mdio_out_from_the_tse_mac;
wire led_an_from_the_tse_mac;
wire led_char_err_from_the_tse_mac;
wire led_col_from_the_tse_mac;
wire led_crs_from_the_tse_mac;
wire led_disp_err_from_the_tse_mac;
wire led_link_from_the_tse_mac;
wire pll_clkin_enet;

wire reconfig_clk_to_the_tse_mac;
wire [4:0] reconfig_fromgxb_from_the_tse_mac;
wire busy; // output not sent from sopc b block
wire [3:0] reconfig_togxb_to_the_tse_mac;

altgx_reconfig altgx_reconfig_inst(
.reconfig_clk (clkin_sys),
.reconfig_fromgxb (reconfig_fromgxb_from_the_tse_mac),
.busy (busy),
.reconfig_togxb (reconfig_togxb_to_the_tse_mac));


ddr_o phy_ckgen(
.datain_h(1'b1),
.datain_l(1'b0),
.outclock(tx_clk_to_the_tse_mac),
.dataout(enet_gtx_clk));

pll_125 this_pll_125 (
.inclk0(clkin_enet),
.c0(pll_clkin_enet));

// PHY interface: need minimum 10ms delay for POR

parameter MSB = 20;

reg [MSB:0] epcount; // 21 bits (2 exp 21) * 20ns = ~42ms

always @(posedge clkin_sys)
begin
if (cpu_resetn == 1'b0)
epcount <= MSB+1'b0;
else
if (epcount[MSB] == 1'b0)
epcount <= epcount +1;
else
epcount <= epcount;
end

assign enet_resetn = !epcount[MSB-1]; // phy held low for ~21 msec after cpu_reset
assign enet_mdio = (mdio_oen_from_the_tse_mac == 1'b0)? mdio_out_from_the_tse_mac : 1'bz;
assign mdio_in_to_the_tse_mac = enet_mdio;

c4gx15_starter_bup_sopc c4gx15_fpga_bup_sopc_inst
(
.chipselect_to_the_tristate_lcd (lcd_csn),
.flash_tristate_bridge_address (fsml_a),
.flash_tristate_bridge_data (fsml_d),
.flash_tristate_bridge_readn (fsml_oen),
.flash_tristate_bridge_writen (fsml_wen),
.select_n_to_the_ext_flash (flash_cen),
.cs_n_to_the_maxII_interface (max2_csn),
.ssram_bwn_to_the_ssram (ssram_bwn),
.ssram_cen_to_the_ssram (ssram_cen),
.in_port_to_the_button_pio (user_pb),
.out_port_from_the_led_pio (user_led),
.mdc_from_the_tse_mac (enet_mdc),
.mdio_in_to_the_tse_mac (mdio_in_to_the_tse_mac),
.mdio_oen_from_the_tse_mac (mdio_oen_from_the_tse_mac),
.mdio_out_from_the_tse_mac (mdio_out_from_the_tse_mac),
//.led_an_from_the_tse_mac (led_an_from_the_tse_mac),
//.led_char_err_from_the_tse_mac (led_char_err_from_the_tse_mac),
//.led_col_from_the_tse_mac (led_col_from_the_tse_mac),
//.led_crs_from_the_tse_mac (led_crs_from_the_tse_mac),
//.led_disp_err_from_the_tse_mac (led_disp_err_from_the_tse_mac),
//.led_link_from_the_tse_mac (led_link_from_the_tse_mac),

//.gxb_cal_blk_clk_to_the_tse_mac (pll_clkin_enet),
//.reconfig_clk_to_the_tse_mac (clkin_sys),
//.reconfig_fromgxb_from_the_tse_mac (reconfig_fromgxb_from_the_tse_mac),
//.reconfig_togxb_to_the_tse_mac (reconfig_togxb_to_the_tse_mac),

//.ref_clk_to_the_tse_mac (pll_clkin_enet), //cascading PLL is not allow, QII v10.1
//.ref_clk_to_the_tse_mac (clkin_enet), //take 125MHz directly from refclk pin
//.txp_from_the_tse_mac (enet_tx),
//.rxp_to_the_tse_mac (enet_rx),

/*
// ethernet
output [ 7: 0] gm_tx_d_from_the_tse_mac;
output gm_tx_en_from_the_tse_mac;
output gm_tx_err_from_the_tse_mac;
input [ 7: 0] gm_rx_d_to_the_tse_mac;
input gm_rx_dv_to_the_tse_mac;
input gm_rx_err_to_the_tse_mac;
input rx_clk_to_the_tse_mac;
input set_1000_to_the_tse_mac;
input set_10_to_the_tse_mac;
input tx_clk_to_the_tse_mac;
*/
.set_1000_to_the_tse_mac(set_1000_to_the_tse_mac),
.set_10_to_the_tse_mac(set_10_to_the_tse_mac),
.rx_clk_to_the_tse_mac(rx_clk_to_the_tse_mac),
.tx_clk_to_the_tse_mac(tx_clk_to_the_tse_mac),

.gm_tx_d_from_the_tse_mac(gm_tx_d_from_the_tse_mac),
.gm_tx_en_from_the_tse_mac(gm_tx_en_from_the_tse_mac),
.gm_tx_err_from_the_tse_mac(gm_tx_err_from_the_tse_mac),

.gm_rx_d_to_the_tse_mac(gm_rx_d_to_the_tse_mac),
.gm_rx_dv_to_the_tse_mac(gm_rx_dv_to_the_tse_mac),
.gm_rx_err_to_the_tse_mac(gm_rx_err_to_the_tse_mac),

//--- ethernet

.osc_clk (clkin_sys),
.ssram_clk (ssram_clk),
.reset_n (cpu_resetn)
);

// ethernet PCS

/*
output [7:0] gmii_rx_d;
output gmii_rx_dv;
output gmii_rx_err;
output tx_clk;
output rx_clk;
output set_10;
output set_100;
output set_1000;
output txp;
input [7:0] gmii_tx_d;
input gmii_tx_en;
input gmii_tx_err;
input reset_tx_clk;
input reset_rx_clk;
input clk;
input reset;
input rxp;
input ref_clk;
input gxb_cal_blk_clk;
input reconfig_clk;
input [3:0] reconfig_togxb;
output [16:0] reconfig_fromgxb;
input reconfig_busy;
*/
eth_pcs pcs(

.clk(clkin_sys), //!!! 50 or 125?
.reset(!cpu_resetn), //!!! active 1 or 0?

// MAC
//.(),

.gmii_rx_d(gm_rx_d_to_the_tse_mac),
.gmii_rx_dv(gm_rx_dv_to_the_tse_mac),
.gmii_rx_err(gm_rx_err_to_the_tse_mac),
.gmii_tx_d(gm_tx_d_from_the_tse_mac),
.gmii_tx_en(gm_tx_en_from_the_tse_mac),
.gmii_tx_err(gm_tx_err_from_the_tse_mac),

// misc

.rx_clk(rx_clk_to_the_tse_mac),
.tx_clk(tx_clk_to_the_tse_mac),

//.set_100(1'b0),
.set_10(set_10_to_the_tse_mac),
.set_1000(set_1000_to_the_tse_mac),

// PHY

.gxb_cal_blk_clk(pll_clkin_enet),
.reconfig_clk(clkin_sys),
.reconfig_togxb(reconfig_togxb_to_the_tse_mac),
.reconfig_fromgxb(reconfig_fromgxb_from_the_tse_mac),

.ref_clk(clkin_enet),
.txp(enet_tx),
.rxp(enet_rx)
);

// END, ethernet PCS


endmodule