library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;

entity IO_SPLITTER_LOW is
    port (
        HOLD_in1, HOLD_in2 : in bit := '0';
        DI_in1, DI_in2 : in bit_vector (31 downto 0);
        DI_out : out bit_vector (31 downto 0);
        DO_out1, DO_out2 : out bit_vector (31 downto 0);
        DO_in : in bit_vector (31 downto 0);
        START_in1, START_in2, WnR_in1, WnR_in2 : in bit;
        DONE_1, DONE_2 : out bit;
        START_out, WnR_out, TST : out bit;
        DONE : in bit;
        RESET, CLK : in bit
    );
end IO_SPLITTER_LOW;

architecture pll_type of IO_SPLITTER_LOW is
    type State_Machine is (S0, S1, S2, S3, S4, S5);
    signal mode : State_Machine;
    signal dir, connected, lstart, eof_flag : bit;
begin
    DI_out <= DI_in1 when dir = '0' else DI_in2;
    WnR_out <= WnR_in1 when dir = '0' else WnR_in2;
    DO_out1 <= DO_in;
    DO_out2 <= DO_in;
    DONE_1 <= DONE when connected = '1' and dir = '0' else '0';
    DONE_2 <= DONE when connected = '1' and dir = '1' else '0';
    lstart <= START_in1 when dir = '0' else START_in2;
    START_out <= lstart when connected = '1' else '0';
    
    TST <= '1' when mode = S2 or mode = S3 else '0';
    
    process (connected, DONE)
    begin
        if DONE = '0' and DONE'event then
            eof_flag <= '1';
        end if;
        if connected = '0' then
            eof_flag <= '0';
        end if;
    end process;
    
    process (CLK, RESET)
    begin
        if CLK = '1' and CLK'event then
            case mode is
                when S0 =>
                    if START_in1 = '1' and HOLD_in2 = '0' then
                        mode <= S2;
                    else
                        mode <= S1;
                    end if;
                when S1 =>
                    if START_in2 = '1' and HOLD_in1 = '0' then
                        mode <= S3;
                    else
                        mode <= S0;
                    end if;
                when S2 =>
                    dir <= '0';
                    mode <= S4;
                when S3 =>
                    dir <= '1';
                    mode <= S4;
                when S4 =>
                    connected <= '1';
                    if eof_flag = '1' then
                        mode <= S5;
                    else
                        mode <= S4;
                    end if;
                when others =>
                    connected <= '0';
                    mode <= S0;
            end case;
        end if;
        if RESET = '1' then
            mode <= S0;
            dir <= '0';
            connected <= '0';
        end if;
    end process;
end pll_type;

create_clock -name {clk} -period 50.000 -waveform { 0.000 25.000 } [get_ports {clk}]

derive_pll_clocks

Critical Warning: Timing requirements not met