set_time_format -unit ns

create_clock -name "iF14" -period 71.428 [get_ports {iF14}]

create_generated_clock -name {sPLL126} -source [get_pins {altpll0_inst|altpll_component|pll|inclk[0]}] \
    -multiply_by 9 [get_pins {altpll0_inst|altpll_component|pll|clk[0]}]

set_output_delay -clock {sPLL126} -reference_pin [get_ports {oSDR_CLK}] -max 2.0 [get_ports {oSDR_A[*] oSDR_BA[*] oSDR_RAS oSDR_CAS oSDR_WE oSDR_DQM_L oSDR_DQM_H ioSDR_DQ[*]}]
set_output_delay -clock {sPLL126} -reference_pin [get_ports {oSDR_CLK}] -min -1.0 [get_ports {oSDR_A[*] oSDR_BA[*] oSDR_RAS oSDR_CAS oSDR_WE oSDR_DQM_L oSDR_DQM_H ioSDR_DQ[*]}]

set_input_delay -clock {sPLL126} -reference_pin [get_ports {oSDR_CLK}] -max 2.5 [get_ports {ioSDR_DQ[*]}] -add_delay
set_input_delay -clock {sPLL126} -reference_pin [get_ports {oSDR_CLK}] -min 1.0 [get_ports {ioSDR_DQ[*]}] -add_delay

create_clock -name "iF14clk" -period 71.428ns [get_ports {iF14}]
derive_pll_clocks
set SDRCLK {altpll0_inst|altpll_component|pll|clk[0]}
create_generated_clock -name {PLL126clk} -source $SDRCLK -offset 0.5 [get_ports {oSDR_CLK}]
set_input_delay -clock PLL126clk -max [expr 5.4 + 0.6] [get_ports {ioSDR_DQ[*]}]
set_input_delay -clock PLL126clk -min [expr 2.5 + 0.4] [get_ports {ioSDR_DQ[*]}]
set_output_delay -clock PLL126clk -max [expr 1.5 + 0.6] [get_ports {oSDR_A[*] oSDR_BA[*] oSDR_RAS oSDR_CAS oSDR_WE oSDR_DQM_L oSDR_DQM_H ioSDR_DQ[*]}]
set_output_delay -clock PLL126clk -min [expr 1 - (0.8 + 0.4)] [get_ports {oSDR_A[*] oSDR_BA[*] oSDR_RAS oSDR_CAS oSDR_WE oSDR_DQM_L oSDR_DQM_H ioSDR_DQ[*]}]

altpll0_inst|altpll_component|pll|clk[0]    Generated    7.936    126.01 MHz    0.000    3.968    50.00    1    9                    false    iF14clk    altpll0_inst|altpll_component|pll|inclk[0]    { altpll0_inst|altpll_component|pll|clk[0] }
iF14clk    Base    71.428    14.0 MHz    0.000    35.714                                            { iF14 }
PLL126clk    Generated    7.936    126.01 MHz    0.500    4.468        1    1        0.500            false    altpll0_inst|altpll_component|pll|clk[0]    altpll0_inst|altpll_component|pll|clk[0]    { oSDR_CLK }

PLL126clk    -3.173    -95.956
altpll0_inst|altpll_component|pll|clk[0]    -2.608    -19.867

                        if sMem_Adr(0) = '0' then
                            sMem_Rd <= ioSDR_DQ(7 downto 0);
                        else
                            sMem_Rd <= ioSDR_DQ(15 downto 8);
                        end if;

set_time_format -unit ns
#
create_clock -name {F14clk} -period 71.428 [get_ports {iF14}]
#
derive_pll_clocks

set SDRAM_CLK altpll0_inst|altpll_component|pll|clk[0]


create_generated_clock -name pSDRAM_CLK -source $SDRAM_CLK [get_ports {oSDR_CLK}]
set_clock_groups -exclusive -group [list F14clk $SDRAM_CLK pSDRAM_CLK ]

set_output_delay -clock pSDRAM_CLK -max 1.5  [get_ports {oSDR_A[*] oSDR_BA[*] oSDR_RAS oSDR_CAS oSDR_WE oSDR_DQM_L oSDR_DQM_H ioSDR_DQ[*]}]
set_output_delay -clock pSDRAM_CLK -min -0.2 [get_ports {oSDR_A[*] oSDR_BA[*] oSDR_RAS oSDR_CAS oSDR_WE oSDR_DQM_L oSDR_DQM_H ioSDR_DQ[*]}]

set_input_delay -clock pSDRAM_CLK -max 5.4 [get_ports {ioSDR_DQ[*]}]
set_input_delay -clock pSDRAM_CLK -min 2.5 [get_ports {ioSDR_DQ[*]}]