#define DAVINCI_GPIO_BINTEN    0x01E26008
#define DAVINCI_GPIO_BANK01    0x01E26010
#define DAVINCI_GPIO_BANK23    0x01E26038
#define DAVINCI_GPIO_BANK45    0x01E26060
#define DAVINCI_GPIO_BANK67    0x01E26088
#define DAVINCI_GPIO_BANK89 0x01E260B0

struct davinci_gpio {
    unsigned int dir;
    unsigned int out_data;
    unsigned int set_data;
    unsigned int clr_data;
    unsigned int in_data;
    unsigned int set_rising;
    unsigned int clr_rising;
    unsigned int set_falling;
    unsigned int clr_falling;
    unsigned int intstat;
};

struct davinci_gpio_bank {
    int num_gpio;
    unsigned int irq_num;
    unsigned int irq_mask;
    unsigned long *in_use;
    unsigned long base;
};

#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
#define davinci_gpio_bank89 ((struct davinci_gpio *)DAVINCI_GPIO_BANK89)

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile unsigned UPPID;
    volatile unsigned UPPCR;
    volatile unsigned UPDLB;
    volatile unsigned char RSVD0[4];
    volatile unsigned UPCTL;
    volatile unsigned UPICR;
    volatile unsigned UPIVR;
    volatile unsigned UPTCR;
    volatile unsigned UPISR;
    volatile unsigned UPIER;
    volatile unsigned UPIES;
    volatile unsigned UPIEC;
    volatile unsigned UPEOI;
    volatile unsigned char RSVD1[12];
    volatile unsigned UPID0;
    volatile unsigned UPID1;
    volatile unsigned UPID2;
    volatile unsigned char RSVD2[4];
    volatile unsigned UPIS0;
    volatile unsigned UPIS1;
    volatile unsigned UPIS2;
    volatile unsigned char RSVD3[4];
    volatile unsigned UPQD0;
    volatile unsigned UPQD1;
    volatile unsigned UPQD2;
    volatile unsigned char RSVD4[4];
    volatile unsigned UPQS0;
    volatile unsigned UPQS1;
    volatile unsigned UPQS2;
} CSL_UppRegs;

typedef struct  {
    volatile unsigned REVID;
    volatile unsigned char RSVD0[4];
    volatile unsigned DIEIDR0;
    volatile unsigned DIEIDR1;
    volatile unsigned DIEIDR2;
    volatile unsigned DIEIDR3;
    volatile unsigned DEVIDR0;
    volatile unsigned char RSVD1[4];
    volatile unsigned BOOTCFG;
    volatile unsigned CHIPREVIDR;
    volatile unsigned char RSVD2[16];
    volatile unsigned KICK0R;
    volatile unsigned KICK1R;
    volatile unsigned HOST0CFG;
    volatile unsigned HOST1CFG1;
    volatile unsigned char RSVD3[152];
    volatile unsigned IRAWSTAT;
    volatile unsigned IENSTAT;
    volatile unsigned IENSET;
    volatile unsigned IENCLR;
    volatile unsigned EOI;
    volatile unsigned FLTADDRR;
    volatile unsigned FLTSTAT;
    volatile unsigned char RSVD4[20];
    volatile unsigned MSTPRI0;
    volatile unsigned MSTPRI1;
    volatile unsigned MSTPRI2;
    volatile unsigned char RSVD5[4];
    volatile unsigned PINMUX0;
    volatile unsigned PINMUX1;
    volatile unsigned PINMUX2;
    volatile unsigned PINMUX3;
    volatile unsigned PINMUX4;
    volatile unsigned PINMUX5;
    volatile unsigned PINMUX6;
    volatile unsigned PINMUX7;
    volatile unsigned PINMUX8;
    volatile unsigned PINMUX9;
    volatile unsigned PINMUX10;
    volatile unsigned PINMUX11;
    volatile unsigned PINMUX12;
    volatile unsigned PINMUX13;
    volatile unsigned PINMUX14;
    volatile unsigned PINMUX15;
    volatile unsigned PINMUX16;
    volatile unsigned PINMUX17;
    volatile unsigned PINMUX18;
    volatile unsigned PINMUX19;
    volatile unsigned SUSPSRC;
    volatile unsigned CHIPSIG;
    volatile unsigned CHIPSIG_CLR;
    volatile unsigned CFGCHIP0;
    volatile unsigned CFGCHIP1;
    volatile unsigned CFGCHIP2;
    volatile unsigned CFGCHIP31;
    volatile unsigned CFGCHIP4;
} CSL_SyscfgRegs;

#define CSL_SYSCFG_0_REGS   (0x01C14000u)
#define CSL_UPP_0_REGS         (0x01E16000u)
CSL_UppRegs* uppRegs =     (CSL_UppRegs*)(CSL_UPP_0_REGS);
CSL_SyscfgRegs* sysRegs = (CSL_SyscfgRegs*)(CSL_SYSCFG_0_REGS);

void UPP_WAITB_RESET(void)
{
    davinci_gpio_bank89->clr_data |= (1<<12);   //WAIT_B off
}

void setup_UPP(void)
{
    int x;
    sysRegs->SUSPSRC &= ~(1<<4);
    //2.1.add. Transmit Clock source - from UPP_2xTXCLK pin
    sysRegs->CFGCHIP31 = 0x60;
/*     uPP Transmit Clock Selection (spruh77.pdf p.144)
CFGCHIP3_UPP_TX | CFGCHIP3_ASYNC3_CLKSRC | Transmit Clock Source
----------------------------------------------------------------
  0 (ASYNC3)    |        0 (PLL0)        |     PLL0_SYSCLK2
  0 (ASYNC3)    |        1 (PLL1)        |     PLL1_SYSCLK2
  1 (TXCLK)     |        X               |     UPP_2xTXCLK pin
*/
    //2.2 Enable clocks uPP
    // Setup Peripherals;
    // wait for UPPID to become valid after enabling module in 2
    while ( uppRegs->UPPID != 0x44231100 );

    //3. SWRST
    //wait for dma active/pending bits DB to clear
    uppRegs->UPPCR = 0x1b;

    //4. Wait at least 200 clock cycles
    udelay(100000);
    uppRegs->UPPCR = 0x0b;

    //5. Program UPP Config Reg's
    //UPCTL
    uppRegs->UPCTL = 0x07;

    //UPICR
    /* !NB
       spruh77.pdf page 1519
       33.2.6.1 Step-by-Step Procedure
       NOTE: When initializing the uPP peripheral, the uPP interface configuration
       register (UPICR) must be programmed using a single, 32-bit write. Writing
       UPICR fields one-by-one can lead to unexpected results.
    */

    uppRegs->UPICR = 0x00180020;

    //UPIVR - idle value
    uppRegs->UPIVR = 0xAC;

    //6. UPIES - Interrupt Enable

    uppRegs->UPIEC = 0xffffffff;
    uppRegs->UPIES = 0x1f1f;
    uppRegs->UPIER = 0xffffffff;

    //7. uPP peripheral Enable
    uppRegs->UPPCR = 0x0b;

    davinci_gpio_bank89->dir &= ~(1<<12);    // wait_b out

    UPP_WAITB_RESET();
}