// System Clocks initialization
void system_clocks_init(void)
{
unsigned char n,s;

// Optimize for speed
#pragma optsize-
// Save interrupts enabled/disabled state
s=SREG;
// Disable interrupts
#asm("cli")

// External 8000.000 kHz clock source on XTAL1 initialization
OSC.XOSCCTRL=OSC_XOSCSEL_EXTCLK_gc;
// Enable the external clock source
OSC.CTRL|=OSC_XOSCEN_bm;

// System Clock prescaler A division factor: 1
// System Clock prescalers B & C division factors: B:2, C:2
// ClkPer4: 128000.000 kHz
// ClkPer2: 64000.000 kHz
// ClkPer: 32000.000 kHz
// ClkCPU: 32000.000 kHz
n=(CLK.PSCTRL & (~(CLK_PSADIV_gm | CLK_PSBCDIV1_bm | CLK_PSBCDIV0_bm))) |
CLK_PSADIV_1_gc | CLK_PSBCDIV_2_2_gc;
CCP=CCP_IOREG_gc;
CLK.PSCTRL=n;

// PLL initialization
// PLL clock source: External Osc. or Clock
// PLL multiplication factor: 16
// PLL frequency: 128.000000 MHz
// Set the PLL clock source and multiplication factor
n=(OSC.PLLCTRL & (~(OSC_PLLSRC_gm | OSC_PLLFAC_gm))) |
OSC_PLLSRC_XOSC_gc | 16;
CCP=CCP_IOREG_gc;
OSC.PLLCTRL=n;
// Enable the PLL
OSC.CTRL|=OSC_PLLEN_bm;

// System Clock prescaler A division factor: 1
// System Clock prescalers B & C division factors: B:2, C:2
// ClkPer4: 128000.000 kHz
// ClkPer2: 64000.000 kHz
// ClkPer: 32000.000 kHz
// ClkCPU: 32000.000 kHz
n=(CLK.PSCTRL & (~(CLK_PSADIV_gm | CLK_PSBCDIV1_bm | CLK_PSBCDIV0_bm))) |
CLK_PSADIV_1_gc | CLK_PSBCDIV_2_2_gc;
CCP=CCP_IOREG_gc;
CLK.PSCTRL=n;

// Wait for the PLL to stabilize
while ((OSC.STATUS & OSC_PLLRDY_bm)==0);

// Select the system clock source: Phase Locked Loop
n=(CLK.CTRL & (~CLK_SCLKSEL_gm)) | CLK_SCLKSEL_PLL_gc;
CCP=CCP_IOREG_gc;
CLK.CTRL=n;

// Disable the unused oscillators: 2 MHz, 32 MHz, internal 32 kHz
OSC.CTRL&= ~(OSC_RC2MEN_bm | OSC_RC32MEN_bm | OSC_RC32KEN_bm);

// ClkPer output: Disabled bit 7
PORTCFG.CLKEVOUT=(PORTCFG.CLKEVOUT & (~PORTCFG_CLKOUT_gm)) | PORTCFG_CLKOUT_OFF_gc;

// Restore interrupts enabled/disabled state
SREG=s;
// Restore optimization for size if needed
#pragma optsize_default
}