проект - скелет вычислителя в котором на данный момент собраны только устройства, отвечающие за "перегонку" данных. однако в уцф-нике описаны все пины, которые будут и, соответственно на топ-лвл-е все эти пины присутствуют. половина из них висит в воздухе. так же некоторые порты уже собранных устройств повешены на землю ввиду отсутствия источников сигналов. из-за этого много сообщений типа - такой то сигнал - нулевая константа, итд.
да, я собираю проект из чужих блоков, поэтому не знаю всех тонкостей каждого отдельно взятого элемента..
CODE
-->
Reading design: SNK_OU.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "SNK_OU.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "SNK_OU"
Output Format : NGC
Target Device : xc6vlx195t-1-ff1156
---- Source Options
Top Module Name : SNK_OU
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : NO
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : NO
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/write_channel.vhd" into library work
Parsing entity <write_channel>.
Parsing architecture <Behavioral> of entity <write_channel>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/SPI/Block_SPI_2LINE.vhd" into library work
Parsing entity <Block_SPI_2LINE>.
Parsing architecture <Behavioral> of entity <block_spi_2line>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/SPI/Block_AMBA_slave.vhd" into library work
Parsing entity <Block_AMBA_AXI_slave>.
Parsing architecture <Behavioral> of entity <block_amba_axi_slave>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd" into library work
Parsing entity <read_channel>.
Parsing architecture <Behavioral> of entity <read_channel>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/shifter_i.vhd" into library work
Parsing entity <shifter_i>.
Parsing architecture <Behavioral> of entity <shifter_i>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RG_D2.vhd" into library work
Parsing entity <RG_D2>.
Parsing architecture <Behavioral> of entity <rg_d2>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RG_D1.vhd" into library work
Parsing entity <RG_D1>.
Parsing architecture <Behavioral> of entity <rg_d1>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RAMB_1Kx64.vhd" into library work
Parsing entity <RAMB_1Kx64>.
Parsing architecture <Behavioral> of entity <ramb_1kx64>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RAMB_1Kx32.vhd" into library work
Parsing entity <RAMB_1Kx32>.
Parsing architecture <Behavioral> of entity <ramb_1kx32>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/PPK.vhd" into library work
Parsing entity <PPK>.
Parsing architecture <Behavioral> of entity <ppk>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/ct_n.vhd" into library work
Parsing entity <ct_n>.
Parsing architecture <Behavioral> of entity <ct_n>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/CT_AK.vhd" into library work
Parsing entity <CT_AK>.
Parsing architecture <Behavioral> of entity <ct_ak>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/comp_0.vhd" into library work
Parsing entity <comp_0>.
Parsing architecture <Behavioral> of entity <comp_0>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/CC22CLED.vhd" into library work
Parsing entity <CC22CLED>.
Parsing architecture <Behavioral> of entity <cc22cled>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/CC10CLED.vhd" into library work
Parsing entity <CC10CLED>.
Parsing architecture <Behavioral> of entity <cc10cled>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/BU_BUSok.vhd" into library work
Parsing entity <BU_BUSok>.
Parsing architecture <Behavioral> of entity <bu_busok>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/ALU_I_v6.vhf" into library work
Parsing entity <M2_1_HXILINX_ALU_I_v6>.
Parsing architecture <M2_1_HXILINX_ALU_I_v6_V> of entity <m2_1_hxilinx_alu_i_v6>.
Parsing entity <ALU_I_v6>.
Parsing architecture <BEHAVIORAL> of entity <alu_i_v6>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/AXI_SPI_2_LINE.vhf" into library work
Parsing entity <AXI_SPI_2_LINE>.
Parsing architecture <BEHAVIORAL> of entity <axi_spi_2_line>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/SLAVE_K.vhd" into library work
Parsing entity <SLAVE_K>.
Parsing architecture <Behavioral> of entity <slave_k>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/RESET_block.vhd" into library work
Parsing entity <RESET_block>.
Parsing architecture <Behavioral> of entity <reset_block>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/LVDS_block.vhd" into library work
Parsing entity <LVDS_block>.
Parsing architecture <Behavioral> of entity <lvds_block>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/Kontr_QDR_OU_AXI.vhd" into library work
Parsing entity <Kontr_QDR_OU_AXI>.
Parsing architecture <Behavioral> of entity <kontr_qdr_ou_axi>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/interconnect.vhd" into library work
Parsing entity <interconnect>.
Parsing architecture <Behavioral> of entity <interconnect>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/ETH_WRITE.vhd" into library work
Parsing entity <ETH_WRITE>.
Parsing architecture <Behavioral> of entity <eth_write>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" into library work
Parsing entity <M2_1_HXILINX_BUSok>.
Parsing architecture <M2_1_HXILINX_BUSok_V> of entity <m2_1_hxilinx_busok>.
Parsing entity <ALU_I_v6_MUSER_BUSok>.
Parsing architecture <BEHAVIORAL> of entity <alu_i_v6_muser_busok>.
Parsing entity <BUSok>.
Parsing architecture <BEHAVIORAL> of entity <busok>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/BUF_block.vhd" into library work
Parsing entity <BUF_block>.
Parsing architecture <Behavioral> of entity <buf_block>.
Parsing VHDL file "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" into library work
Parsing entity <SNK_OU>.
Parsing architecture <BEHAVIORAL> of entity <snk_ou>.
CODE
=======================================================================
==
* HDL Elaboration *
=========================================================================
Elaborating entity <SNK_OU> (architecture <BEHAVIORAL>) from library <work>.
Elaborating entity <BUF_block> (architecture <Behavioral>) from library <work>.
Elaborating entity <LVDS_block> (architecture <Behavioral>) from library <work>.
Elaborating entity <RESET_block> (architecture <Behavioral>) from library <work>.
Elaborating entity <interconnect> (architecture <Behavioral>) from library <work>.
Elaborating entity <write_channel> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/write_channel.vhd" Line 180: Assignment to end_transfer_d ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/write_channel.vhd" Line 275: Assignment to awready_2d ignored, since the identifier is never used
Elaborating entity <read_channel> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd" Line 115: Assignment to end_transferm1_r ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd" Line 116: Assignment to end_transferm2_r ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd" Line 117: Assignment to end_transferm3_r ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd" Line 153: Assignment to bl_arvalid_d ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd" Line 388: Assignment to rid_3d ignored, since the identifier is never used
Elaborating entity <Kontr_QDR_OU_AXI> (architecture <Behavioral>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/Kontr_QDR_OU_AXI.vhd" Line 127: Assignment to arvalid_2d ignored, since the identifier is never used
Elaborating entity <AXI_SPI_2_LINE> (architecture <BEHAVIORAL>) from library <work>.
Elaborating entity <Block_AMBA_AXI_slave> (architecture <Behavioral>) from library <work>.
Elaborating entity <Block_SPI_2LINE> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/SPI/Block_SPI_2LINE.vhd" Line 156: Assignment to kd_0_d1 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/gayver/Project Xilinx/Project/SNK_OU/SPI/Block_SPI_2LINE.vhd" Line 797: Assignment to pch1_d1_p ignored, since the identifier is never used
Elaborating entity <BUSok> (architecture <BEHAVIORAL>) from library <work>.
Elaborating entity <CT_AK> (architecture <Behavioral>) from library <work>.
Elaborating entity <ALU_I_v6_MUSER_BUSok> (architecture <BEHAVIORAL>) from library <work>.
Elaborating entity <M2_1_HXILINX_BUSok> (architecture <M2_1_HXILINX_BUSok_V>) from library <work>.
INFO:HDLCompiler:679 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" Line 44. Case statement is complete. others clause is never selected
Elaborating entity <BU_BUSok> (architecture <Behavioral>) from library <work>.
Elaborating entity <comp_0> (architecture <Behavioral>) from library <work>.
Elaborating entity <CC22CLED> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <CC10CLED> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <ct_n> (architecture <Behavioral>) from library <work>.
Elaborating entity <RAMB_1Kx32> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <RAMB_1Kx64> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <PPK> (architecture <Behavioral>) from library <work>.
Elaborating entity <RG_D1> (architecture <Behavioral>) from library <work>.
Elaborating entity <RG_D2> (architecture <Behavioral>) from library <work>.
Elaborating entity <shifter_i> (architecture <Behavioral>) from library <work>.
Elaborating entity <ETH_WRITE> (architecture <Behavioral>) from library <work>.
Elaborating entity <SLAVE_K> (architecture <Behavioral>) from library <work>.
WARNING:HDLCompiler:634 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" Line 288: Net <RREADY_m1> does not have a driver.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <SNK_OU>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf".
Set property "BANDWIDTH = OPTIMIZED" for instance <XLXI_38>.
Set property "CLKFBOUT_MULT_F = 24.0" for instance <XLXI_38>.
Set property "CLKFBOUT_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLKIN1_PERIOD = 20.0" for instance <XLXI_38>.
Set property "CLKOUT0_DIVIDE_F = 6.0" for instance <XLXI_38>.
Set property "CLKOUT0_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT0_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLKOUT1_DIVIDE = 6" for instance <XLXI_38>.
Set property "CLKOUT1_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT1_PHASE = 270.0" for instance <XLXI_38>.
Set property "CLKOUT2_DIVIDE = 1" for instance <XLXI_38>.
Set property "CLKOUT2_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT2_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLKOUT3_DIVIDE = 8" for instance <XLXI_38>.
Set property "CLKOUT3_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT3_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLKOUT4_CASCADE = FALSE" for instance <XLXI_38>.
Set property "CLKOUT4_DIVIDE = 1" for instance <XLXI_38>.
Set property "CLKOUT4_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT4_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLKOUT5_DIVIDE = 1" for instance <XLXI_38>.
Set property "CLKOUT5_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT5_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLKOUT6_DIVIDE = 1" for instance <XLXI_38>.
Set property "CLKOUT6_DUTY_CYCLE = 0.500" for instance <XLXI_38>.
Set property "CLKOUT6_PHASE = 0.000" for instance <XLXI_38>.
Set property "CLOCK_HOLD = FALSE" for instance <XLXI_38>.
Set property "DIVCLK_DIVIDE = 1" for instance <XLXI_38>.
Set property "REF_JITTER1 = 0.010" for instance <XLXI_38>.
Set property "STARTUP_WAIT = FALSE" for instance <XLXI_38>.
WARNING:Xst:647 - Input <AP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BUS_PDCL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CD_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CD_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CSMCU> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CTS_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CTS_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DSR_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DSR_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <F_ADC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OCHM_ETH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <OCHM_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PPDS_ETH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PVDS_ETH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RI_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RI_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RXD_0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RXD_1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RXFM_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RXFS_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SCLKMCU> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SDIMCU> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SYNC_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <TXEM_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <TXES_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <U0_OCHS_ETH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <U0_OCHS_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Z_OCHS_ETH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Z_OCHS_USB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 795: Output port <d_out_usbm> of the instance <B_BUF> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 795: Output port <d_out_usbs> of the instance <B_BUF> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 795: Output port <d_out_eths> of the instance <B_BUF> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 795: Output port <d_out_izp> of the instance <B_BUF> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 876: Output port <AWID> of the instance <inter_slave0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 876: Output port <RDATAm3> of the instance <inter_slave0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 876: Output port <ARREADYm3> of the instance <inter_slave0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 876: Output port <RVALIDm3> of the instance <inter_slave0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 876: Output port <AWREADYm3> of the instance <inter_slave0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 876: Output port <WREADYm3> of the instance <inter_slave0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 937: Output port <AWID> of the instance <inter_slave1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 937: Output port <RDATAm3> of the instance <inter_slave1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 937: Output port <ARREADYm3> of the instance <inter_slave1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 937: Output port <RVALIDm3> of the instance <inter_slave1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 937: Output port <AWREADYm3> of the instance <inter_slave1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 937: Output port <WREADYm3> of the instance <inter_slave1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 998: Output port <AWID> of the instance <inter_slave7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 998: Output port <RDATAm3> of the instance <inter_slave7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 998: Output port <ARREADYm3> of the instance <inter_slave7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 998: Output port <RVALIDm3> of the instance <inter_slave7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 998: Output port <AWREADYm3> of the instance <inter_slave7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 998: Output port <WREADYm3> of the instance <inter_slave7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1059: Output port <AWID> of the instance <inter_slave8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1059: Output port <RDATAm3> of the instance <inter_slave8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1059: Output port <ARREADYm3> of the instance <inter_slave8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1059: Output port <RVALIDm3> of the instance <inter_slave8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1059: Output port <AWREADYm3> of the instance <inter_slave8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1059: Output port <WREADYm3> of the instance <inter_slave8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1120: Output port <AWID> of the instance <inter_slave41> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1120: Output port <RDATAm3> of the instance <inter_slave41> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1120: Output port <ARREADYm3> of the instance <inter_slave41> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1120: Output port <RVALIDm3> of the instance <inter_slave41> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1120: Output port <AWREADYm3> of the instance <inter_slave41> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1120: Output port <WREADYm3> of the instance <inter_slave41> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1181: Output port <DATA_BVV> of the instance <K_QDR_RAM1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1181: Output port <OCH_WR> of the instance <K_QDR_RAM1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1181: Output port <OCH_RD> of the instance <K_QDR_RAM1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1181: Output port <STROB_BVV> of the instance <K_QDR_RAM1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1223: Output port <DATA_BVV> of the instance <K_QDR_RAM2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1223: Output port <OCH_WR> of the instance <K_QDR_RAM2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1223: Output port <OCH_RD> of the instance <K_QDR_RAM2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1223: Output port <STROB_BVV> of the instance <K_QDR_RAM2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1265: Output port <DATA_BVV> of the instance <K_QDR_RAM3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1265: Output port <OCH_WR> of the instance <K_QDR_RAM3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1265: Output port <OCH_RD> of the instance <K_QDR_RAM3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1265: Output port <STROB_BVV> of the instance <K_QDR_RAM3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1307: Output port <DATA_BVV> of the instance <K_QDR_RAM4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1307: Output port <OCH_WR> of the instance <K_QDR_RAM4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1307: Output port <OCH_RD> of the instance <K_QDR_RAM4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1307: Output port <STROB_BVV> of the instance <K_QDR_RAM4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1349: Output port <BRESP> of the instance <K_SPI_OU1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1349: Output port <RRESP> of the instance <K_SPI_OU1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1349: Output port <BVALID> of the instance <K_SPI_OU1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1374: Output port <WSTRB> of the instance <M1_BUS> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1374: Output port <BREADY> of the instance <M1_BUS> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1374: Output port <RREADY> of the instance <M1_BUS> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1397: Output port <AWPROT> of the instance <M2_ETH> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1397: Output port <WSTRB> of the instance <M2_ETH> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1397: Output port <BREADY> of the instance <M2_ETH> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1397: Output port <ARPROT> of the instance <M2_ETH> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKFBOUTB> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT0B> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT1B> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT2> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT2B> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT3B> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT4> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT5> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <CLKOUT6> of the instance <XLXI_38> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/SNK_OU.vhf" line 1594: Output port <LOCKED> of the instance <XLXI_38> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <RREADY_m1> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Summary:
no macro.
Unit <SNK_OU> synthesized.
CODE
Synthesizing Unit <BUF_block>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUF_block.vhd".
WARNING:Xst:647 - Input <d_in_eths<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Summary:
no macro.
Unit <BUF_block> synthesized.
Synthesizing Unit <LVDS_block>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/LVDS_block.vhd".
Summary:
no macro.
Unit <LVDS_block> synthesized.
Synthesizing Unit <RESET_block>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/RESET_block.vhd".
Summary:
no macro.
Unit <RESET_block> synthesized.
Synthesizing Unit <interconnect>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/interconnect.vhd".
Summary:
no macro.
Unit <interconnect> synthesized.
Synthesizing Unit <write_channel>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/write_channel.vhd".
Found 1-bit register for signal <bl_wreadym1>.
Found 1-bit register for signal <bl_awreadym2>.
Found 1-bit register for signal <bl_wreadym2>.
Found 1-bit register for signal <bl_awreadym3>.
Found 1-bit register for signal <bl_wreadym3>.
Found 1-bit register for signal <bl_awready>.
Found 1-bit register for signal <bl_wready>.
Found 1-bit register for signal <hold_channel>.
Found 1-bit register for signal <bl_wready_d>.
Found 1-bit register for signal <awvalidm1_d>.
Found 1-bit register for signal <awvalidm1_2d>.
Found 1-bit register for signal <awvalidm2_d>.
Found 1-bit register for signal <awvalidm2_2d>.
Found 1-bit register for signal <awvalidm3_d>.
Found 1-bit register for signal <awvalidm3_2d>.
Found 1-bit register for signal <awvalidm1_2d_dt>.
Found 1-bit register for signal <awvalidm2_2d_dt>.
Found 1-bit register for signal <awvalidm3_2d_dt>.
Found 26-bit register for signal <awaddrm1_d>.
Found 26-bit register for signal <awaddrm1_2d>.
Found 26-bit register for signal <awaddrm2_d>.
Found 26-bit register for signal <awaddrm2_2d>.
Found 26-bit register for signal <awaddrm3_d>.
Found 26-bit register for signal <awaddrm3_2d>.
Found 3-bit register for signal <n_channel_w>.
Found 3-bit register for signal <n_channel_data>.
Found 1-bit register for signal <awready_d>.
Found 1-bit register for signal <falling_awready>.
Found 1-bit register for signal <rising_awready_d>.
Found 26-bit register for signal <awaddrs_m2d>.
Found 1-bit register for signal <awvalids_m2d>.
Found 26-bit register for signal <awaddrs_md>.
Found 1-bit register for signal <awvalids_md>.
Found 3-bit register for signal <n_channel_wn_d>.
Found 3-bit register for signal <n_channel_datan_d>.
Found 1-bit register for signal <new_ch_adr_d>.
Found 1-bit register for signal <new_ch_adr_2d>.
Found 1-bit register for signal <new_ch_adr_3d>.
Found 1-bit register for signal <new_ch_adr_4d>.
Found 1-bit register for signal <new_ch_adr_5d>.
Found 1-bit register for signal <new_ch_data_d>.
Found 1-bit register for signal <new_ch_data_2d>.
Found 1-bit register for signal <new_ch_data_3d>.
Found 1-bit register for signal <new_ch_data_4d>.
Found 1-bit register for signal <new_ch_data_5d>.
Found 1-bit register for signal <wvalidm1_d>.
Found 1-bit register for signal <wvalidm1_2d>.
Found 1-bit register for signal <wvalidm2_d>.
Found 1-bit register for signal <wvalidm2_2d>.
Found 1-bit register for signal <wvalidm3_d>.
Found 1-bit register for signal <wvalidm3_2d>.
Found 32-bit register for signal <wdatam1_d>.
Found 32-bit register for signal <wdatam1_2d>.
Found 32-bit register for signal <wdatam2_d>.
Found 32-bit register for signal <wdatam2_2d>.
Found 32-bit register for signal <wdatam3_d>.
Found 32-bit register for signal <wdatam3_2d>.
Found 1-bit register for signal <wready_d>.
Found 1-bit register for signal <falling_wready>.
Found 1-bit register for signal <rising_wready_d>.
Found 32-bit register for signal <wdatas_m2d>.
Found 1-bit register for signal <wvalids_m2d>.
Found 32-bit register for signal <wdatas_md>.
Found 1-bit register for signal <wvalids_md>.
Found 1-bit register for signal <och1w>.
Found 1-bit register for signal <och2w>.
Found 1-bit register for signal <flag1w>.
Found 1-bit register for signal <flag2w>.
Found 1-bit register for signal <awready_internal>.
Found 1-bit register for signal <wready_internal>.
Found 1-bit register for signal <awvalids_tmp>.
Found 1-bit register for signal <wvalids_tmp>.
Found 1-bit register for signal <awvalids_tmp_d>.
Found 1-bit register for signal <wvalids_tmp_d>.
Found 26-bit register for signal <awaddrs_tmp>.
Found 32-bit register for signal <wdatas_tmp>.
Found 1-bit register for signal <AWREADYm1>.
Found 1-bit register for signal <WREADYm1>.
Found 1-bit register for signal <AWREADYm2>.
Found 1-bit register for signal <WREADYm2>.
Found 1-bit register for signal <AWREADYm3>.
Found 1-bit register for signal <WREADYm3>.
Found 4-bit register for signal <AWID>.
Found 1-bit register for signal <awreadym1_internal>.
Found 1-bit register for signal <wreadym1_internal>.
Found 1-bit register for signal <awreadym2_internal>.
Found 1-bit register for signal <wreadym2_internal>.
Found 1-bit register for signal <awreadym3_internal>.
Found 1-bit register for signal <wreadym3_internal>.
Found 1-bit register for signal <bl_awreadym1>.
Found 6-bit comparator equal for signal <cmp_ustr_w_m1> created at line 176
Found 6-bit comparator equal for signal <cmp_ustr_w_m2> created at line 177
Found 6-bit comparator equal for signal <cmp_ustr_w_m3> created at line 178
Summary:
inferred 605 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 48 Multiplexer(s).
Unit <write_channel> synthesized.
Synthesizing Unit <read_channel>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/read_chennal.vhd".
Found 1-bit register for signal <bl_arreadym2>.
Found 1-bit register for signal <bl_arreadym3>.
Found 1-bit register for signal <bl_arready>.
Found 1-bit register for signal <ust_rready>.
Found 1-bit register for signal <bl_rvalids>.
Found 1-bit register for signal <rvalids_dt>.
Found 1-bit register for signal <bl_arready_d>.
Found 1-bit register for signal <arvalidm1_d>.
Found 1-bit register for signal <arvalidm1_2d>.
Found 1-bit register for signal <arvalidm2_d>.
Found 1-bit register for signal <arvalidm2_2d>.
Found 1-bit register for signal <arvalidm3_d>.
Found 1-bit register for signal <arvalidm3_2d>.
Found 1-bit register for signal <arvalidm1_2d_dt>.
Found 1-bit register for signal <arvalidm2_2d_dt>.
Found 1-bit register for signal <arvalidm3_2d_dt>.
Found 26-bit register for signal <araddrm1_d>.
Found 26-bit register for signal <araddrm1_2d>.
Found 26-bit register for signal <araddrm2_d>.
Found 26-bit register for signal <araddrm2_2d>.
Found 26-bit register for signal <araddrm3_d>.
Found 26-bit register for signal <araddrm3_2d>.
Found 1-bit register for signal <arready_d>.
Found 1-bit register for signal <falling_arready>.
Found 1-bit register for signal <rising_arready_d>.
Found 26-bit register for signal <araddrs_m2d>.
Found 1-bit register for signal <arvalids_m2d>.
Found 26-bit register for signal <araddrs_md>.
Found 1-bit register for signal <arvalids_md>.
Found 3-bit register for signal <n_channel_rn_d>.
Found 1-bit register for signal <new_ch_r_d>.
Found 1-bit register for signal <new_ch_r_2d>.
Found 1-bit register for signal <new_ch_r_3d>.
Found 1-bit register for signal <new_ch_r_4d>.
Found 1-bit register for signal <new_ch_r_5d>.
Found 1-bit register for signal <start_rvalidm3_d>.
Found 1-bit register for signal <start_rvalidm2_d>.
Found 1-bit register for signal <start_rvalidm1_d>.
Found 1-bit register for signal <och1r>.
Found 1-bit register for signal <och2r>.
Found 1-bit register for signal <flag1r>.
Found 1-bit register for signal <flag2r>.
Found 3-bit register for signal <n_channel_r>.
Found 1-bit register for signal <arready_internal>.
Found 32-bit register for signal <rdatas_d>.
Found 32-bit register for signal <rdatas_2d>.
Found 32-bit register for signal <rdatas_3d>.
Found 32-bit register for signal <rdatas_4d>.
Found 1-bit register for signal <rvalids_d>.
Found 1-bit register for signal <rvalids_2d>.
Found 1-bit register for signal <rvalids_3d>.
Found 1-bit register for signal <rvalids_4d>.
Found 1-bit register for signal <rreadym1_d>.
Found 1-bit register for signal <rreadym2_d>.
Found 1-bit register for signal <rreadym3_d>.
Found 1-bit register for signal <start_d>.
Found 1-bit register for signal <rising_rreadym1_d>.
Found 1-bit register for signal <rising_rreadym2_d>.
Found 1-bit register for signal <rising_rreadym3_d>.
Found 1-bit register for signal <falling_rreadym1>.
Found 1-bit register for signal <falling_rreadym2>.
Found 1-bit register for signal <falling_rreadym3>.
Found 1-bit register for signal <arvalids_tmp>.
Found 1-bit register for signal <arvalids_tmp_d>.
Found 26-bit register for signal <araddrs_tmp>.
Found 1-bit register for signal <ARREADYm1>.
Found 1-bit register for signal <ARREADYm2>.
Found 1-bit register for signal <ARREADYm3>.
Found 4-bit register for signal <ARID>.
Found 1-bit register for signal <arreadym1_internal>.
Found 1-bit register for signal <arreadym2_internal>.
Found 1-bit register for signal <arreadym3_internal>.
Found 3-bit register for signal <rid_tmp>.
Found 32-bit register for signal <RDATAm1>.
Found 1-bit register for signal <rvalidm1_tmp>.
Found 32-bit register for signal <RDATAm2>.
Found 1-bit register for signal <rvalidm2_tmp>.
Found 32-bit register for signal <RDATAm3>.
Found 1-bit register for signal <rvalidm3_tmp>.
Found 1-bit register for signal <rreadys_tmp>.
Found 1-bit register for signal <rreadys_internal>.
Found 1-bit register for signal <rvalidm1_tmp_d>.
Found 1-bit register for signal <rvalidm2_tmp_d>.
Found 1-bit register for signal <rvalidm3_tmp_d>.
Found 1-bit register for signal <bl_arreadym1>.
Found 6-bit comparator equal for signal <cmp_ustr_r_m1> created at line 141
Found 6-bit comparator equal for signal <cmp_ustr_r_m2> created at line 142
Found 6-bit comparator equal for signal <cmp_ustr_r_m3> created at line 143
Summary:
inferred 536 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 49 Multiplexer(s).
Unit <read_channel> synthesized.
Synthesizing Unit <Kontr_QDR_OU_AXI>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/Kontr_QDR_OU_AXI.vhd".
depth = 5
depth_zap = 5
depth_op = 7
depth2 = 6
WARNING:Xst:647 - Input <AWADDR<31:23>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AWADDR<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARADDR<31:23>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARADDR<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <bl_awvalid>.
Found 1-bit register for signal <wready_tmp>.
Found 1-bit register for signal <bl_wvalid>.
Found 1-bit register for signal <zapros_och_wr_d>.
Found 1-bit register for signal <zapros_och_wr_2d>.
Found 1-bit register for signal <zapros_och_wr_3d>.
Found 1-bit register for signal <zapros_och_rd_d>.
Found 1-bit register for signal <zapros_och_rd_2d>.
Found 1-bit register for signal <zapros_och_rd_3d>.
Found 1-bit register for signal <awvalid_d>.
Found 1-bit register for signal <awvalid_2d>.
Found 1-bit register for signal <awready_d>.
Found 1-bit register for signal <awready_2d>.
Found 1-bit register for signal <STROB_BVV>.
Found 32-bit register for signal <DATA_BVV>.
Found 1-bit register for signal <end_op>.
Found 1-bit register for signal <och_rd_tmp>.
Found 1-bit register for signal <och_wr_tmp>.
Found 21-bit register for signal <write_addr>.
Found 21-bit register for signal <read_addr>.
Found 32-bit register for signal <data_wr>.
Found 1-bit register for signal <wr_qdr>.
Found 1-bit register for signal <rd_qdr>.
Found 1-bit register for signal <rd_ram>.
Found 1-bit register for signal <rvalid_tmp>.
Found 1-bit register for signal <arready_tmp>.
Found 1-bit register for signal <rising_arvalid_sh_d>.
Found 6-bit register for signal <rising_arvalid_sh>.
Found 6-bit register for signal <falling_arvalid_sh>.
Found 6-bit register for signal <t_zap_conv>.
Found 32-bit register for signal <conv_data<6>>.
Found 32-bit register for signal <conv_data<5>>.
Found 32-bit register for signal <conv_data<4>>.
Found 32-bit register for signal <conv_data<3>>.
Found 32-bit register for signal <conv_data<2>>.
Found 32-bit register for signal <conv_data<1>>.
Found 32-bit register for signal <conv_data<0>>.
Found 7-bit register for signal <falling_arvalid_sh_ce>.
Found 8-bit register for signal <t_op_conv>.
Found 32-bit register for signal <RDATA>.
Found 1-bit register for signal <conv>.
Found 1-bit register for signal <zap_conv>.
Found 1-bit register for signal <op_conv>.
Found 4-bit register for signal <id_in>.
Found 4-bit register for signal <RID>.
Found 1-bit register for signal <arvalid_d>.
Found 1-bit register for signal <arready_d>.
Found 1-bit register for signal <awready_tmp>.
Summary:
inferred 432 D-type flip-flop(s).
inferred 12 Multiplexer(s).
Unit <Kontr_QDR_OU_AXI> synthesized.
Synthesizing Unit <AXI_SPI_2_LINE>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/AXI_SPI_2_LINE.vhf".
Summary:
no macro.
Unit <AXI_SPI_2_LINE> synthesized.
Synthesizing Unit <Block_AMBA_AXI_slave>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/SPI/Block_AMBA_slave.vhd".
WARNING:Xst:647 - Input <AWADDR<31:24>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AWADDR<22:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <AWADDR<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARADDR<31:24>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARADDR<22:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ARADDR<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 4-bit register for signal <ARID_s>.
Found 2-bit register for signal <RRESP>.
Found 1-bit register for signal <BVALID>.
Found 1-bit register for signal <datazap>.
Found 1-bit register for signal <RD>.
Found 1-bit register for signal <WR_s>.
Found 1-bit register for signal <PROC_stop_d>.
Found 1-bit register for signal <PROC_stop_d1>.
Found 1-bit register for signal <PROC_stop_d2>.
Found 5-bit register for signal <s_SHADR_R>.
Found 1-bit register for signal <ARREADY_s>.
Found 1-bit register for signal <adr_l>.
Found 5-bit register for signal <s_SHADR>.
Found 1-bit register for signal <data_l>.
Found 32-bit register for signal <SHD_TO_OUT>.
Found 1-bit register for signal <AWREADY_s>.
Found 1-bit register for signal <WREADY_s>.
Found 1-bit register for signal <RVALID_s>.
Found 4-bit register for signal <RID>.
Found 2-bit register for signal <BRESP>.
Summary:
inferred 67 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <Block_AMBA_AXI_slave> synthesized.
CODE
Synthesizing Unit <Block_SPI_2LINE>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/SPI/Block_SPI_2LINE.vhd".
WARNING:Xst:647 - Input <CLR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 16-bit register for signal <RG_KD>.
Found 5-bit register for signal <RG_Kbit>.
Found 5-bit register for signal <RG_Kbit_symbol>.
Found 32-bit register for signal <RGD_out>.
Found 32-bit register for signal <RGS_out>.
Found 4-bit register for signal <count_t>.
Found 5-bit register for signal <COUNT_Kbit>.
Found 5-bit register for signal <COUNT_Kbit_symbol>.
Found 16-bit register for signal <COUNT_KD>.
Found 1-bit register for signal <start_sclk>.
Found 1-bit register for signal <OD>.
Found 8-bit register for signal <RG_com>.
Found 8-bit register for signal <RG_com_isp>.
Found 1-bit register for signal <data_got_s>.
Found 1-bit register for signal <KD_0>.
Found 1-bit register for signal <KD_0_data>.
Found 1-bit register for signal <s_P_in>.
Found 1-bit register for signal <s_P_out>.
Found 1-bit register for signal <P_in>.
Found 1-bit register for signal <P_out>.
Found 1-bit register for signal <s_RGD_out_busy>.
Found 1-bit register for signal <s_RG_com_busy>.
Found 1-bit register for signal <s_RGD_in_ready_d0>.
Found 1-bit register for signal <RGD_in_zap>.
Found 8-bit register for signal <status>.
Found 1-bit register for signal <sclk_tmp>.
Found 1-bit register for signal <perepol>.
Found 1-bit register for signal <P_in_d1>.
Found 1-bit register for signal <s_RG_loaded>.
Found 32-bit register for signal <SHD_TO_IN>.
Found 1-bit register for signal <s_RGD_in_ready>.
Found 1-bit register for signal <data_delay>.
Found 1-bit register for signal <process_stoped>.
Found 1-bit register for signal <com_in>.
Found 1-bit register for signal <com_out>.
Found 1-bit register for signal <Pch0>.
Found 1-bit register for signal <Pch1>.
Found 1-bit register for signal <T0>.
Found 1-bit register for signal <T0_in>.
Found 1-bit register for signal <T_in>.
Found 1-bit register for signal <T>.
Found 32-bit register for signal <RGS_in>.
Found 1-bit register for signal <read_enable>.
Found 32-bit register for signal <RGD_in>.
Found 5-bit register for signal <RG_tp_kc>.
Found 4-bit adder for signal <count_t[3]_GND_813_o_add_0_OUT> created at line 196.
Found 5-bit subtractor for signal <GND_813_o_GND_813_o_sub_66_OUT<4:0>> created at line 300.
Found 5-bit subtractor for signal <GND_813_o_GND_813_o_sub_123_OUT<4:0>> created at line 418.
Found 16-bit subtractor for signal <GND_813_o_GND_813_o_sub_176_OUT<15:0>> created at line 550.
Found 1-bit 4-to-1 multiplexer for signal <GND_813_o_count_t[0]_MUX_654_o> created at line 806.
Summary:
inferred 4 Adder/Subtractor(s).
inferred 274 D-type flip-flop(s).
inferred 1220 Multiplexer(s).
Unit <Block_SPI_2LINE> synthesized.
Synthesizing Unit <BUSok>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf".
Set property "HU_SET = XLXI_11_0_191" for instance <XLXI_11_0>.
Set property "HU_SET = XLXI_11_1_190" for instance <XLXI_11_1>.
Set property "HU_SET = XLXI_11_2_189" for instance <XLXI_11_2>.
Set property "HU_SET = XLXI_11_3_188" for instance <XLXI_11_3>.
Set property "HU_SET = XLXI_11_4_187" for instance <XLXI_11_4>.
Set property "HU_SET = XLXI_11_5_186" for instance <XLXI_11_5>.
Set property "HU_SET = XLXI_11_6_185" for instance <XLXI_11_6>.
Set property "HU_SET = XLXI_11_7_184" for instance <XLXI_11_7>.
Set property "HU_SET = XLXI_11_8_183" for instance <XLXI_11_8>.
Set property "HU_SET = XLXI_11_9_182" for instance <XLXI_11_9>.
Set property "HU_SET = XLXI_11_10_181" for instance <XLXI_11_10>.
Set property "HU_SET = XLXI_11_11_180" for instance <XLXI_11_11>.
Set property "HU_SET = XLXI_11_12_179" for instance <XLXI_11_12>.
Set property "HU_SET = XLXI_11_13_178" for instance <XLXI_11_13>.
Set property "HU_SET = XLXI_11_14_177" for instance <XLXI_11_14>.
Set property "HU_SET = XLXI_11_15_176" for instance <XLXI_11_15>.
Set property "HU_SET = XLXI_11_16_175" for instance <XLXI_11_16>.
Set property "HU_SET = XLXI_11_17_174" for instance <XLXI_11_17>.
Set property "HU_SET = XLXI_11_18_173" for instance <XLXI_11_18>.
Set property "HU_SET = XLXI_11_19_172" for instance <XLXI_11_19>.
Set property "HU_SET = XLXI_11_20_171" for instance <XLXI_11_20>.
Set property "HU_SET = XLXI_11_21_170" for instance <XLXI_11_21>.
Set property "HU_SET = XLXI_11_22_169" for instance <XLXI_11_22>.
Set property "HU_SET = XLXI_11_23_168" for instance <XLXI_11_23>.
Set property "HU_SET = XLXI_11_24_167" for instance <XLXI_11_24>.
Set property "HU_SET = XLXI_11_25_166" for instance <XLXI_11_25>.
Set property "HU_SET = XLXI_11_26_165" for instance <XLXI_11_26>.
Set property "HU_SET = XLXI_11_27_164" for instance <XLXI_11_27>.
Set property "HU_SET = XLXI_11_28_163" for instance <XLXI_11_28>.
Set property "HU_SET = XLXI_11_29_162" for instance <XLXI_11_29>.
Set property "HU_SET = XLXI_11_30_161" for instance <XLXI_11_30>.
Set property "HU_SET = XLXI_11_31_160" for instance <XLXI_11_31>.
Set property "HU_SET = XLXI_11_32_159" for instance <XLXI_11_32>.
Set property "HU_SET = XLXI_11_33_158" for instance <XLXI_11_33>.
Set property "HU_SET = XLXI_11_34_157" for instance <XLXI_11_34>.
Set property "HU_SET = XLXI_11_35_156" for instance <XLXI_11_35>.
Set property "HU_SET = XLXI_11_36_155" for instance <XLXI_11_36>.
Set property "HU_SET = XLXI_11_37_154" for instance <XLXI_11_37>.
Set property "HU_SET = XLXI_11_38_153" for instance <XLXI_11_38>.
Set property "HU_SET = XLXI_11_39_152" for instance <XLXI_11_39>.
Set property "HU_SET = XLXI_11_40_151" for instance <XLXI_11_40>.
Set property "HU_SET = XLXI_11_41_150" for instance <XLXI_11_41>.
Set property "HU_SET = XLXI_11_42_149" for instance <XLXI_11_42>.
Set property "HU_SET = XLXI_11_43_148" for instance <XLXI_11_43>.
Set property "HU_SET = XLXI_11_44_147" for instance <XLXI_11_44>.
Set property "HU_SET = XLXI_11_45_146" for instance <XLXI_11_45>.
Set property "HU_SET = XLXI_11_46_145" for instance <XLXI_11_46>.
Set property "HU_SET = XLXI_11_47_144" for instance <XLXI_11_47>.
Set property "HU_SET = XLXI_11_48_143" for instance <XLXI_11_48>.
Set property "HU_SET = XLXI_11_49_142" for instance <XLXI_11_49>.
Set property "HU_SET = XLXI_11_50_141" for instance <XLXI_11_50>.
Set property "HU_SET = XLXI_11_51_140" for instance <XLXI_11_51>.
Set property "HU_SET = XLXI_11_52_139" for instance <XLXI_11_52>.
Set property "HU_SET = XLXI_11_53_138" for instance <XLXI_11_53>.
Set property "HU_SET = XLXI_11_54_137" for instance <XLXI_11_54>.
Set property "HU_SET = XLXI_11_55_136" for instance <XLXI_11_55>.
Set property "HU_SET = XLXI_11_56_135" for instance <XLXI_11_56>.
Set property "HU_SET = XLXI_11_57_134" for instance <XLXI_11_57>.
Set property "HU_SET = XLXI_11_58_133" for instance <XLXI_11_58>.
Set property "HU_SET = XLXI_11_59_132" for instance <XLXI_11_59>.
Set property "HU_SET = XLXI_11_60_131" for instance <XLXI_11_60>.
Set property "HU_SET = XLXI_11_61_130" for instance <XLXI_11_61>.
Set property "HU_SET = XLXI_11_62_129" for instance <XLXI_11_62>.
Set property "HU_SET = XLXI_11_63_128" for instance <XLXI_11_63>.
Set property "HU_SET = XLXI_654_0_201" for instance <XLXI_654_0>.
Set property "HU_SET = XLXI_654_1_200" for instance <XLXI_654_1>.
Set property "HU_SET = XLXI_654_2_199" for instance <XLXI_654_2>.
Set property "HU_SET = XLXI_654_3_198" for instance <XLXI_654_3>.
Set property "HU_SET = XLXI_654_4_197" for instance <XLXI_654_4>.
Set property "HU_SET = XLXI_654_5_196" for instance <XLXI_654_5>.
Set property "HU_SET = XLXI_654_6_195" for instance <XLXI_654_6>.
Set property "HU_SET = XLXI_654_7_194" for instance <XLXI_654_7>.
Set property "HU_SET = XLXI_654_8_193" for instance <XLXI_654_8>.
Set property "HU_SET = XLXI_654_9_192" for instance <XLXI_654_9>.
Set property "HU_SET = XLXI_655_0_211" for instance <XLXI_655_0>.
Set property "HU_SET = XLXI_655_1_210" for instance <XLXI_655_1>.
Set property "HU_SET = XLXI_655_2_209" for instance <XLXI_655_2>.
Set property "HU_SET = XLXI_655_3_208" for instance <XLXI_655_3>.
Set property "HU_SET = XLXI_655_4_207" for instance <XLXI_655_4>.
Set property "HU_SET = XLXI_655_5_206" for instance <XLXI_655_5>.
Set property "HU_SET = XLXI_655_6_205" for instance <XLXI_655_6>.
Set property "HU_SET = XLXI_655_7_204" for instance <XLXI_655_7>.
Set property "HU_SET = XLXI_655_8_203" for instance <XLXI_655_8>.
Set property "HU_SET = XLXI_655_9_202" for instance <XLXI_655_9>.
Set property "HU_SET = XLXI_658_0_221" for instance <XLXI_658_0>.
Set property "HU_SET = XLXI_658_1_220" for instance <XLXI_658_1>.
Set property "HU_SET = XLXI_658_2_219" for instance <XLXI_658_2>.
Set property "HU_SET = XLXI_658_3_218" for instance <XLXI_658_3>.
Set property "HU_SET = XLXI_658_4_217" for instance <XLXI_658_4>.
Set property "HU_SET = XLXI_658_5_216" for instance <XLXI_658_5>.
Set property "HU_SET = XLXI_658_6_215" for instance <XLXI_658_6>.
Set property "HU_SET = XLXI_658_7_214" for instance <XLXI_658_7>.
Set property "HU_SET = XLXI_658_8_213" for instance <XLXI_658_8>.
Set property "HU_SET = XLXI_658_9_212" for instance <XLXI_658_9>.
Set property "HU_SET = XLXI_741_0_253" for instance <XLXI_741_0>.
Set property "HU_SET = XLXI_741_1_252" for instance <XLXI_741_1>.
Set property "HU_SET = XLXI_741_2_251" for instance <XLXI_741_2>.
Set property "HU_SET = XLXI_741_3_250" for instance <XLXI_741_3>.
Set property "HU_SET = XLXI_741_4_249" for instance <XLXI_741_4>.
Set property "HU_SET = XLXI_741_5_248" for instance <XLXI_741_5>.
Set property "HU_SET = XLXI_741_6_247" for instance <XLXI_741_6>.
Set property "HU_SET = XLXI_741_7_246" for instance <XLXI_741_7>.
Set property "HU_SET = XLXI_741_8_245" for instance <XLXI_741_8>.
Set property "HU_SET = XLXI_741_9_244" for instance <XLXI_741_9>.
Set property "HU_SET = XLXI_741_10_243" for instance <XLXI_741_10>.
Set property "HU_SET = XLXI_741_11_242" for instance <XLXI_741_11>.
Set property "HU_SET = XLXI_741_12_241" for instance <XLXI_741_12>.
Set property "HU_SET = XLXI_741_13_240" for instance <XLXI_741_13>.
Set property "HU_SET = XLXI_741_14_239" for instance <XLXI_741_14>.
Set property "HU_SET = XLXI_741_15_238" for instance <XLXI_741_15>.
Set property "HU_SET = XLXI_741_16_237" for instance <XLXI_741_16>.
Set property "HU_SET = XLXI_741_17_236" for instance <XLXI_741_17>.
Set property "HU_SET = XLXI_741_18_235" for instance <XLXI_741_18>.
Set property "HU_SET = XLXI_741_19_234" for instance <XLXI_741_19>.
Set property "HU_SET = XLXI_741_20_233" for instance <XLXI_741_20>.
Set property "HU_SET = XLXI_741_21_232" for instance <XLXI_741_21>.
Set property "HU_SET = XLXI_741_22_231" for instance <XLXI_741_22>.
Set property "HU_SET = XLXI_741_23_230" for instance <XLXI_741_23>.
Set property "HU_SET = XLXI_741_24_229" for instance <XLXI_741_24>.
Set property "HU_SET = XLXI_741_25_228" for instance <XLXI_741_25>.
Set property "HU_SET = XLXI_741_26_227" for instance <XLXI_741_26>.
Set property "HU_SET = XLXI_741_27_226" for instance <XLXI_741_27>.
Set property "HU_SET = XLXI_741_28_225" for instance <XLXI_741_28>.
Set property "HU_SET = XLXI_741_29_224" for instance <XLXI_741_29>.
Set property "HU_SET = XLXI_741_30_223" for instance <XLXI_741_30>.
Set property "HU_SET = XLXI_741_31_222" for instance <XLXI_741_31>.
Set property "HU_SET = XLXI_742_0_285" for instance <XLXI_742_0>.
Set property "HU_SET = XLXI_742_1_284" for instance <XLXI_742_1>.
Set property "HU_SET = XLXI_742_2_283" for instance <XLXI_742_2>.
Set property "HU_SET = XLXI_742_3_282" for instance <XLXI_742_3>.
Set property "HU_SET = XLXI_742_4_281" for instance <XLXI_742_4>.
Set property "HU_SET = XLXI_742_5_280" for instance <XLXI_742_5>.
Set property "HU_SET = XLXI_742_6_279" for instance <XLXI_742_6>.
Set property "HU_SET = XLXI_742_7_278" for instance <XLXI_742_7>.
Set property "HU_SET = XLXI_742_8_277" for instance <XLXI_742_8>.
Set property "HU_SET = XLXI_742_9_276" for instance <XLXI_742_9>.
Set property "HU_SET = XLXI_742_10_275" for instance <XLXI_742_10>.
Set property "HU_SET = XLXI_742_11_274" for instance <XLXI_742_11>.
Set property "HU_SET = XLXI_742_12_273" for instance <XLXI_742_12>.
Set property "HU_SET = XLXI_742_13_272" for instance <XLXI_742_13>.
Set property "HU_SET = XLXI_742_14_271" for instance <XLXI_742_14>.
Set property "HU_SET = XLXI_742_15_270" for instance <XLXI_742_15>.
Set property "HU_SET = XLXI_742_16_269" for instance <XLXI_742_16>.
Set property "HU_SET = XLXI_742_17_268" for instance <XLXI_742_17>.
Set property "HU_SET = XLXI_742_18_267" for instance <XLXI_742_18>.
Set property "HU_SET = XLXI_742_19_266" for instance <XLXI_742_19>.
Set property "HU_SET = XLXI_742_20_265" for instance <XLXI_742_20>.
Set property "HU_SET = XLXI_742_21_264" for instance <XLXI_742_21>.
Set property "HU_SET = XLXI_742_22_263" for instance <XLXI_742_22>.
Set property "HU_SET = XLXI_742_23_262" for instance <XLXI_742_23>.
Set property "HU_SET = XLXI_742_24_261" for instance <XLXI_742_24>.
Set property "HU_SET = XLXI_742_25_260" for instance <XLXI_742_25>.
Set property "HU_SET = XLXI_742_26_259" for instance <XLXI_742_26>.
Set property "HU_SET = XLXI_742_27_258" for instance <XLXI_742_27>.
Set property "HU_SET = XLXI_742_28_257" for instance <XLXI_742_28>.
Set property "HU_SET = XLXI_742_29_256" for instance <XLXI_742_29>.
Set property "HU_SET = XLXI_742_30_255" for instance <XLXI_742_30>.
Set property "HU_SET = XLXI_742_31_254" for instance <XLXI_742_31>.
Set property "HU_SET = XLXI_744_0_317" for instance <XLXI_744_0>.
Set property "HU_SET = XLXI_744_1_316" for instance <XLXI_744_1>.
Set property "HU_SET = XLXI_744_2_315" for instance <XLXI_744_2>.
Set property "HU_SET = XLXI_744_3_314" for instance <XLXI_744_3>.
Set property "HU_SET = XLXI_744_4_313" for instance <XLXI_744_4>.
Set property "HU_SET = XLXI_744_5_312" for instance <XLXI_744_5>.
Set property "HU_SET = XLXI_744_6_311" for instance <XLXI_744_6>.
Set property "HU_SET = XLXI_744_7_310" for instance <XLXI_744_7>.
Set property "HU_SET = XLXI_744_8_309" for instance <XLXI_744_8>.
Set property "HU_SET = XLXI_744_9_308" for instance <XLXI_744_9>.
Set property "HU_SET = XLXI_744_10_307" for instance <XLXI_744_10>.
Set property "HU_SET = XLXI_744_11_306" for instance <XLXI_744_11>.
Set property "HU_SET = XLXI_744_12_305" for instance <XLXI_744_12>.
Set property "HU_SET = XLXI_744_13_304" for instance <XLXI_744_13>.
Set property "HU_SET = XLXI_744_14_303" for instance <XLXI_744_14>.
Set property "HU_SET = XLXI_744_15_302" for instance <XLXI_744_15>.
Set property "HU_SET = XLXI_744_16_301" for instance <XLXI_744_16>.
Set property "HU_SET = XLXI_744_17_300" for instance <XLXI_744_17>.
Set property "HU_SET = XLXI_744_18_299" for instance <XLXI_744_18>.
Set property "HU_SET = XLXI_744_19_298" for instance <XLXI_744_19>.
Set property "HU_SET = XLXI_744_20_297" for instance <XLXI_744_20>.
Set property "HU_SET = XLXI_744_21_296" for instance <XLXI_744_21>.
Set property "HU_SET = XLXI_744_22_295" for instance <XLXI_744_22>.
Set property "HU_SET = XLXI_744_23_294" for instance <XLXI_744_23>.
Set property "HU_SET = XLXI_744_24_293" for instance <XLXI_744_24>.
Set property "HU_SET = XLXI_744_25_292" for instance <XLXI_744_25>.
Set property "HU_SET = XLXI_744_26_291" for instance <XLXI_744_26>.
Set property "HU_SET = XLXI_744_27_290" for instance <XLXI_744_27>.
Set property "HU_SET = XLXI_744_28_289" for instance <XLXI_744_28>.
Set property "HU_SET = XLXI_744_29_288" for instance <XLXI_744_29>.
Set property "HU_SET = XLXI_744_30_287" for instance <XLXI_744_30>.
Set property "HU_SET = XLXI_744_31_286" for instance <XLXI_744_31>.
Set property "HU_SET = XLXI_751_0_323" for instance <XLXI_751_0>.
Set property "HU_SET = XLXI_751_1_322" for instance <XLXI_751_1>.
Set property "HU_SET = XLXI_751_2_321" for instance <XLXI_751_2>.
Set property "HU_SET = XLXI_751_3_320" for instance <XLXI_751_3>.
Set property "HU_SET = XLXI_751_4_319" for instance <XLXI_751_4>.
Set property "HU_SET = XLXI_751_5_318" for instance <XLXI_751_5>.
Set property "HU_SET = XLXI_758_0_355" for instance <XLXI_758_0>.
Set property "HU_SET = XLXI_758_1_354" for instance <XLXI_758_1>.
Set property "HU_SET = XLXI_758_2_353" for instance <XLXI_758_2>.
Set property "HU_SET = XLXI_758_3_352" for instance <XLXI_758_3>.
Set property "HU_SET = XLXI_758_4_351" for instance <XLXI_758_4>.
Set property "HU_SET = XLXI_758_5_350" for instance <XLXI_758_5>.
Set property "HU_SET = XLXI_758_6_349" for instance <XLXI_758_6>.
Set property "HU_SET = XLXI_758_7_348" for instance <XLXI_758_7>.
Set property "HU_SET = XLXI_758_8_347" for instance <XLXI_758_8>.
Set property "HU_SET = XLXI_758_9_346" for instance <XLXI_758_9>.
Set property "HU_SET = XLXI_758_10_345" for instance <XLXI_758_10>.
Set property "HU_SET = XLXI_758_11_344" for instance <XLXI_758_11>.
Set property "HU_SET = XLXI_758_12_343" for instance <XLXI_758_12>.
Set property "HU_SET = XLXI_758_13_342" for instance <XLXI_758_13>.
Set property "HU_SET = XLXI_758_14_341" for instance <XLXI_758_14>.
Set property "HU_SET = XLXI_758_15_340" for instance <XLXI_758_15>.
Set property "HU_SET = XLXI_758_16_339" for instance <XLXI_758_16>.
Set property "HU_SET = XLXI_758_17_338" for instance <XLXI_758_17>.
Set property "HU_SET = XLXI_758_18_337" for instance <XLXI_758_18>.
Set property "HU_SET = XLXI_758_19_336" for instance <XLXI_758_19>.
Set property "HU_SET = XLXI_758_20_335" for instance <XLXI_758_20>.
Set property "HU_SET = XLXI_758_21_334" for instance <XLXI_758_21>.
Set property "HU_SET = XLXI_758_22_333" for instance <XLXI_758_22>.
Set property "HU_SET = XLXI_758_23_332" for instance <XLXI_758_23>.
Set property "HU_SET = XLXI_758_24_331" for instance <XLXI_758_24>.
Set property "HU_SET = XLXI_758_25_330" for instance <XLXI_758_25>.
Set property "HU_SET = XLXI_758_26_329" for instance <XLXI_758_26>.
Set property "HU_SET = XLXI_758_27_328" for instance <XLXI_758_27>.
Set property "HU_SET = XLXI_758_28_327" for instance <XLXI_758_28>.
Set property "HU_SET = XLXI_758_29_326" for instance <XLXI_758_29>.
Set property "HU_SET = XLXI_758_30_325" for instance <XLXI_758_30>.
Set property "HU_SET = XLXI_758_31_324" for instance <XLXI_758_31>.
Set property "HU_SET = XLXI_762_0_377" for instance <XLXI_762_0>.
Set property "HU_SET = XLXI_762_1_376" for instance <XLXI_762_1>.
Set property "HU_SET = XLXI_762_2_375" for instance <XLXI_762_2>.
Set property "HU_SET = XLXI_762_3_374" for instance <XLXI_762_3>.
Set property "HU_SET = XLXI_762_4_373" for instance <XLXI_762_4>.
Set property "HU_SET = XLXI_762_5_372" for instance <XLXI_762_5>.
Set property "HU_SET = XLXI_762_6_371" for instance <XLXI_762_6>.
Set property "HU_SET = XLXI_762_7_370" for instance <XLXI_762_7>.
Set property "HU_SET = XLXI_762_8_369" for instance <XLXI_762_8>.
Set property "HU_SET = XLXI_762_9_368" for instance <XLXI_762_9>.
Set property "HU_SET = XLXI_762_10_367" for instance <XLXI_762_10>.
Set property "HU_SET = XLXI_762_11_366" for instance <XLXI_762_11>.
Set property "HU_SET = XLXI_762_12_365" for instance <XLXI_762_12>.
Set property "HU_SET = XLXI_762_13_364" for instance <XLXI_762_13>.
Set property "HU_SET = XLXI_762_14_363" for instance <XLXI_762_14>.
Set property "HU_SET = XLXI_762_15_362" for instance <XLXI_762_15>.
Set property "HU_SET = XLXI_762_16_361" for instance <XLXI_762_16>.
Set property "HU_SET = XLXI_762_17_360" for instance <XLXI_762_17>.
Set property "HU_SET = XLXI_762_18_359" for instance <XLXI_762_18>.
Set property "HU_SET = XLXI_762_19_358" for instance <XLXI_762_19>.
Set property "HU_SET = XLXI_762_20_357" for instance <XLXI_762_20>.
Set property "HU_SET = XLXI_762_21_356" for instance <XLXI_762_21>.
WARNING:Xst:647 - Input <BRESP<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RRESP<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 1858: Output port <TC> of the instance <CT_A> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 1868: Output port <TC> of the instance <CT_A1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 1878: Output port <TC> of the instance <CT_A2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4316: Output port <Q> of the instance <XLXI_740_22> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4321: Output port <Q> of the instance <XLXI_740_23> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4326: Output port <Q> of the instance <XLXI_740_24> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4331: Output port <Q> of the instance <XLXI_740_25> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4336: Output port <Q> of the instance <XLXI_740_26> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4341: Output port <Q> of the instance <XLXI_740_27> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4346: Output port <Q> of the instance <XLXI_740_28> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4351: Output port <Q> of the instance <XLXI_740_29> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4356: Output port <Q> of the instance <XLXI_740_30> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 4361: Output port <Q> of the instance <XLXI_740_31> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <BUSok> synthesized.
CODE
Synthesizing Unit <CT_AK>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/CT_AK.vhd".
Found 10-bit register for signal <tmp>.
Found 1-bit register for signal <q_tmp<10>>.
Found 10-bit adder for signal <tmp[9]_GND_815_o_add_2_OUT> created at line 74.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 11 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <CT_AK> synthesized.
Synthesizing Unit <ALU_I_v6_MUSER_BUSok>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf".
Set property "HU_SET = XLXI_872_0_95" for instance <XLXI_872_0>.
Set property "HU_SET = XLXI_872_1_94" for instance <XLXI_872_1>.
Set property "HU_SET = XLXI_872_2_93" for instance <XLXI_872_2>.
Set property "HU_SET = XLXI_872_3_92" for instance <XLXI_872_3>.
Set property "HU_SET = XLXI_872_4_91" for instance <XLXI_872_4>.
Set property "HU_SET = XLXI_872_5_90" for instance <XLXI_872_5>.
Set property "HU_SET = XLXI_872_6_89" for instance <XLXI_872_6>.
Set property "HU_SET = XLXI_872_7_88" for instance <XLXI_872_7>.
Set property "HU_SET = XLXI_872_8_87" for instance <XLXI_872_8>.
Set property "HU_SET = XLXI_872_9_86" for instance <XLXI_872_9>.
Set property "HU_SET = XLXI_872_10_85" for instance <XLXI_872_10>.
Set property "HU_SET = XLXI_872_11_84" for instance <XLXI_872_11>.
Set property "HU_SET = XLXI_872_12_83" for instance <XLXI_872_12>.
Set property "HU_SET = XLXI_872_13_82" for instance <XLXI_872_13>.
Set property "HU_SET = XLXI_872_14_81" for instance <XLXI_872_14>.
Set property "HU_SET = XLXI_872_15_80" for instance <XLXI_872_15>.
Set property "HU_SET = XLXI_872_16_79" for instance <XLXI_872_16>.
Set property "HU_SET = XLXI_872_17_78" for instance <XLXI_872_17>.
Set property "HU_SET = XLXI_872_18_77" for instance <XLXI_872_18>.
Set property "HU_SET = XLXI_872_19_76" for instance <XLXI_872_19>.
Set property "HU_SET = XLXI_872_20_75" for instance <XLXI_872_20>.
Set property "HU_SET = XLXI_872_21_74" for instance <XLXI_872_21>.
Set property "HU_SET = XLXI_872_22_73" for instance <XLXI_872_22>.
Set property "HU_SET = XLXI_872_23_72" for instance <XLXI_872_23>.
Set property "HU_SET = XLXI_872_24_71" for instance <XLXI_872_24>.
Set property "HU_SET = XLXI_872_25_70" for instance <XLXI_872_25>.
Set property "HU_SET = XLXI_872_26_69" for instance <XLXI_872_26>.
Set property "HU_SET = XLXI_872_27_68" for instance <XLXI_872_27>.
Set property "HU_SET = XLXI_872_28_67" for instance <XLXI_872_28>.
Set property "HU_SET = XLXI_872_29_66" for instance <XLXI_872_29>.
Set property "HU_SET = XLXI_872_30_65" for instance <XLXI_872_30>.
Set property "HU_SET = XLXI_872_31_64" for instance <XLXI_872_31>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_893_0>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_893_1>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_893_2>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_893_3>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_896_0>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_896_1>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_896_2>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_896_3>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_898_0>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_898_1>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_898_2>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_898_3>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_900_0>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_900_1>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_900_2>.
Set property "INIT = 6A66CC00EAEE8866" for instance <XLXI_900_3>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_906_0>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_906_1>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_906_2>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_906_3>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_912_0>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_912_1>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_912_2>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_912_3>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_916_0>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_916_1>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_916_2>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_916_3>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_918_0>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_918_1>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_918_2>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_918_3>.
Set property "INIT = 6A66AA00EAEE8866" for instance <XLXI_928>.
Set property "HU_SET = XLXI_932_0_127" for instance <XLXI_932_0>.
Set property "HU_SET = XLXI_932_1_126" for instance <XLXI_932_1>.
Set property "HU_SET = XLXI_932_2_125" for instance <XLXI_932_2>.
Set property "HU_SET = XLXI_932_3_124" for instance <XLXI_932_3>.
Set property "HU_SET = XLXI_932_4_123" for instance <XLXI_932_4>.
Set property "HU_SET = XLXI_932_5_122" for instance <XLXI_932_5>.
Set property "HU_SET = XLXI_932_6_121" for instance <XLXI_932_6>.
Set property "HU_SET = XLXI_932_7_120" for instance <XLXI_932_7>.
Set property "HU_SET = XLXI_932_8_119" for instance <XLXI_932_8>.
Set property "HU_SET = XLXI_932_9_118" for instance <XLXI_932_9>.
Set property "HU_SET = XLXI_932_10_117" for instance <XLXI_932_10>.
Set property "HU_SET = XLXI_932_11_116" for instance <XLXI_932_11>.
Set property "HU_SET = XLXI_932_12_115" for instance <XLXI_932_12>.
Set property "HU_SET = XLXI_932_13_114" for instance <XLXI_932_13>.
Set property "HU_SET = XLXI_932_14_113" for instance <XLXI_932_14>.
Set property "HU_SET = XLXI_932_15_112" for instance <XLXI_932_15>.
Set property "HU_SET = XLXI_932_16_111" for instance <XLXI_932_16>.
Set property "HU_SET = XLXI_932_17_110" for instance <XLXI_932_17>.
Set property "HU_SET = XLXI_932_18_109" for instance <XLXI_932_18>.
Set property "HU_SET = XLXI_932_19_108" for instance <XLXI_932_19>.
Set property "HU_SET = XLXI_932_20_107" for instance <XLXI_932_20>.
Set property "HU_SET = XLXI_932_21_106" for instance <XLXI_932_21>.
Set property "HU_SET = XLXI_932_22_105" for instance <XLXI_932_22>.
Set property "HU_SET = XLXI_932_23_104" for instance <XLXI_932_23>.
Set property "HU_SET = XLXI_932_24_103" for instance <XLXI_932_24>.
Set property "HU_SET = XLXI_932_25_102" for instance <XLXI_932_25>.
Set property "HU_SET = XLXI_932_26_101" for instance <XLXI_932_26>.
Set property "HU_SET = XLXI_932_27_100" for instance <XLXI_932_27>.
Set property "HU_SET = XLXI_932_28_99" for instance <XLXI_932_28>.
Set property "HU_SET = XLXI_932_29_98" for instance <XLXI_932_29>.
Set property "HU_SET = XLXI_932_30_97" for instance <XLXI_932_30>.
Set property "HU_SET = XLXI_932_31_96" for instance <XLXI_932_31>.
INFO:Xst:3210 - "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf" line 947: Output port <O> of the instance <XLXI_927> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <ALU_I_v6_MUSER_BUSok> synthesized.
Synthesizing Unit <M2_1_HXILINX_BUSok>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSok.vhf".
Summary:
inferred 1 Multiplexer(s).
Unit <M2_1_HXILINX_BUSok> synthesized.
Synthesizing Unit <BU_BUSok>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/BU_BUSok.vhd".
WARNING:Xst:647 - Input <KOP<57:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <KOP<21:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <KOP<9:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <reset_2d>.
Found 1-bit register for signal <zp_rg_k_tmp>.
Found 1-bit register for signal <t1>.
Found 1-bit register for signal <t2>.
Found 1-bit register for signal <t3>.
Found 6-bit register for signal <rg_kop>.
Found 1-bit register for signal <zagr>.
Found 1-bit register for signal <zagr_c>.
Found 1-bit register for signal <vygr>.
Found 1-bit register for signal <vygr_c>.
Found 1-bit register for signal <uost>.
Found 1-bit register for signal <alk>.
Found 1-bit register for signal <vygr_pk>.
Found 1-bit register for signal <massiv>.
Found 1-bit register for signal <bit_27>.
Found 1-bit register for signal <bit_10>.
Found 3-bit register for signal <alk_op>.
Found 1-bit register for signal <tct>.
Found 1-bit register for signal <vo_3d>.
Found 1-bit register for signal <vo_4d>.
Found 1-bit register for signal <vo_5d>.
Found 1-bit register for signal <vo>.
Found 1-bit register for signal <vo_d>.
Found 1-bit register for signal <vo_2d>.
Found 1-bit register for signal <vod>.
Found 1-bit register for signal <vod_d>.
Found 1-bit register for signal <vod_2d>.
Found 1-bit register for signal <vod_3d>.
Found 1-bit register for signal <rg_fi>.
Found 1-bit register for signal <rg_zn>.
Found 1-bit register for signal <rg_zero>.
Found 2-bit register for signal <n_usl>.
Found 1-bit register for signal <delta1>.
Found 1-bit register for signal <delta2>.
Found 1-bit register for signal <delta3>.
Found 1-bit register for signal <delta4>.
Found 1-bit register for signal <delta5>.
Found 1-bit register for signal <x1>.
Found 1-bit register for signal <x2>.
Found 1-bit register for signal <x3>.
Found 1-bit register for signal <ci>.
Found 1-bit register for signal <nakop>.
Found 1-bit register for signal <inv_rg_d2>.
Found 1-bit register for signal <alk_d>.
Found 1-bit register for signal <nop>.
Found 1-bit register for signal <up_d>.
Found 1-bit register for signal <arvalid_tmp>.
Found 1-bit register for signal <rready_tmp>.
Found 1-bit register for signal <awvalid_tmp>.
Found 1-bit register for signal <wvalid_tmp>.
Found 1-bit register for signal <bready_tmp>.
Found 1-bit register for signal <reset_d>.
Summary:
inferred 60 D-type flip-flop(s).
inferred 85 Multiplexer(s).
Unit <BU_BUSok> synthesized.
Synthesizing Unit <comp_0>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/comp_0.vhd".
Summary:
no macro.
Unit <comp_0> synthesized.
Synthesizing Unit <CC22CLED>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/CC22CLED.vhd".
width = 22
Found 22-bit register for signal <COUNT>.
Found 22-bit adder for signal <COUNT[21]_GND_820_o_add_0_OUT> created at line 59.
Found 22-bit subtractor for signal <GND_820_o_GND_820_o_sub_2_OUT<21:0>> created at line 61.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 22 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <CC22CLED> synthesized.
Synthesizing Unit <CC10CLED>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/CC10CLED.vhd".
width = 10
Found 10-bit register for signal <COUNT>.
Found 10-bit adder for signal <COUNT[9]_GND_821_o_add_0_OUT> created at line 59.
Found 10-bit subtractor for signal <GND_821_o_GND_821_o_sub_2_OUT<9:0>> created at line 61.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 10 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <CC10CLED> synthesized.
Synthesizing Unit <ct_n>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/ct_n.vhd".
Found 10-bit register for signal <q_count>.
Found 11-bit subtractor for signal <tmp> created at line 36.
Summary:
inferred 1 Adder/Subtractor(s).
inferred 10 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <ct_n> synthesized.
Synthesizing Unit <RAMB_1Kx32>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RAMB_1Kx32.vhd".
size = 1024
addr_width = 10
di_width = 32
Found 1024x32-bit dual-port RAM <Mram_RAM> for signal <RAM>.
Found 32-bit register for signal <DOB>.
Found 32-bit register for signal <DOA>.
Summary:
inferred 1 RAM(s).
inferred 64 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <RAMB_1Kx32> synthesized.
Synthesizing Unit <RAMB_1Kx64>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RAMB_1Kx64.vhd".
size = 1024
addr_width = 10
di_width = 64
Found 1024x64-bit dual-port RAM <Mram_RAM> for signal <RAM>.
Found 64-bit register for signal <DOB>.
Found 64-bit register for signal <DOA>.
Summary:
inferred 1 RAM(s).
inferred 128 D-type flip-flop(s).
inferred 2 Multiplexer(s).
Unit <RAMB_1Kx64> synthesized.
Synthesizing Unit <PPK>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/PPK.vhd".
Found 64-bit register for signal <Q>.
Found 16x64-bit Read Only RAM for signal <tmp>
Summary:
inferred 1 RAM(s).
inferred 64 D-type flip-flop(s).
Unit <PPK> synthesized.
Synthesizing Unit <RG_D1>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RG_D1.vhd".
Found 32-bit register for signal <q_tmp>.
Summary:
inferred 32 D-type flip-flop(s).
Unit <RG_D1> synthesized.
Synthesizing Unit <RG_D2>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/RG_D2.vhd".
Found 32-bit register for signal <q_tmp>.
Summary:
inferred 32 D-type flip-flop(s).
inferred 1 Multiplexer(s).
Unit <RG_D2> synthesized.
Synthesizing Unit <shifter_i>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/BUSoK/shifter_i.vhd".
Found 35-bit 4-to-1 multiplexer for signal <shift_3> created at line 27.
Found 47-bit 4-to-1 multiplexer for signal <shift_12> created at line 28.
Found 32-bit 32-to-1 multiplexer for signal <dc_const> created at line 25.
Summary:
inferred 8 Multiplexer(s).
Unit <shifter_i> synthesized.
CODE
Synthesizing Unit <ETH_WRITE>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/ETH_WRITE.vhd".
WARNING:Xst:647 - Input <BRESP<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RRESP<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BVALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <WSTRB> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <BREADY> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ARPROT> is used but never assigned. This sourceless signal will be automatically connected to value GND.
Found 1-bit register for signal <kvd2d>.
Found 1-bit register for signal <kpdd>.
Found 1-bit register for signal <kpd2d>.
Found 1-bit register for signal <PPD>.
Found 1-bit register for signal <pvd_tmp>.
Found 1-bit register for signal <shift_stack_out>.
Found 1-bit register for signal <wr_stack_in>.
Found 1-bit register for signal <wr_stack_in_d>.
Found 8-bit register for signal <rg1d>.
Found 8-bit register for signal <rg2d>.
Found 8-bit register for signal <rg3d>.
Found 8-bit register for signal <rg4d>.
Found 8-bit register for signal <rg5d>.
Found 8-bit register for signal <rg6d>.
Found 8-bit register for signal <rg7d>.
Found 8-bit register for signal <rg8d>.
Found 1-bit register for signal <flag_data>.
Found 4-bit register for signal <ct_stack>.
Found 8-bit register for signal <rg_com>.
Found 24-bit register for signal <ct_col_a>.
Found 32-bit register for signal <ct_addr>.
Found 24-bit register for signal <ct_col_d>.
Found 32-bit register for signal <rg_WDATA>.
Found 1-bit register for signal <WVALID_tmp>.
Found 1-bit register for signal <Flag_AWVALID>.
Found 1-bit register for signal <AWVALID>.
Found 1-bit register for signal <ARVALID>.
Found 8-bit register for signal <rg4d_out>.
Found 8-bit register for signal <rg3d_out>.
Found 8-bit register for signal <rg2d_out>.
Found 8-bit register for signal <rg1d_out>.
Found 32-bit register for signal <Rg_RDATA>.
Found 1-bit register for signal <wr_stack_out>.
Found 1-bit register for signal <RREADY_tmp>.
Found 1-bit register for signal <kvdd>.
Found 4-bit adder for signal <ct_stack[3]_GND_831_o_add_23_OUT> created at line 133.
Found 32-bit adder for signal <ct_addr[31]_GND_831_o_add_31_OUT> created at line 155.
Found 24-bit subtractor for signal <GND_831_o_GND_831_o_sub_31_OUT<23:0>> created at line 154.
Found 24-bit subtractor for signal <GND_831_o_GND_831_o_sub_42_OUT<23:0>> created at line 165.
Summary:
inferred 4 Adder/Subtractor(s).
inferred 268 D-type flip-flop(s).
inferred 9 Multiplexer(s).
Unit <ETH_WRITE> synthesized.
Synthesizing Unit <SLAVE_K>.
Related source file is "/home/gayver/Project Xilinx/Project/SNK_OU/SLAVE_K.vhd".
Summary:
no macro.
Unit <SLAVE_K> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 3
1024x32-bit dual-port RAM : 1
1024x64-bit dual-port RAM : 1
16x64-bit single-port Read Only RAM : 1
# Adders/Subtractors : 14
10-bit adder : 1
10-bit addsub : 3
11-bit subtractor : 1
16-bit subtractor : 1
22-bit addsub : 1
24-bit subtractor : 2
32-bit adder : 1
4-bit adder : 2
5-bit subtractor : 2
# Registers : 1228
1-bit register : 884
10-bit register : 5
16-bit register : 2
2-bit register : 3
21-bit register : 8
22-bit register : 1
24-bit register : 3
26-bit register : 90
3-bit register : 36
32-bit register : 134
4-bit register : 22
5-bit register : 7
6-bit register : 13
64-bit register : 3
7-bit register : 4
8-bit register : 13
# Comparators : 30
6-bit comparator equal : 30
# Multiplexers : 2183
1-bit 2-to-1 multiplexer : 825
1-bit 4-to-1 multiplexer : 1
10-bit 2-to-1 multiplexer : 6
16-bit 2-to-1 multiplexer : 6
2-bit 2-to-1 multiplexer : 1
21-bit 2-to-1 multiplexer : 8
22-bit 2-to-1 multiplexer : 1
24-bit 2-to-1 multiplexer : 4
26-bit 2-to-1 multiplexer : 60
3-bit 2-to-1 multiplexer : 45
32-bit 2-to-1 multiplexer : 131
32-bit 32-to-1 multiplexer : 1
35-bit 4-to-1 multiplexer : 1
47-bit 4-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1079
64-bit 2-to-1 multiplexer : 2
7-bit 2-to-1 multiplexer : 8
8-bit 2-to-1 multiplexer : 3
# Xors : 45
1-bit xor2 : 45
CODE
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <rvalidm1_tmp> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bl_arreadym2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ust_rready> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rising_rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ARID_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_4> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_5> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_6> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_7> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_8> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_9> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_10> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_11> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_12> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_13> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_14> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_15> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_16> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_17> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_18> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_4> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_5> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_6> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_7> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_8> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_9> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_10> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_11> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_12> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_13> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_14> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_15> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_16> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_17> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_18> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_19> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_20> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_21> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_22> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_23> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_24> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_25> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_26> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_27> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_28> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_29> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_30> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_31> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_7> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_8> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_9> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_10> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_11> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_12> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_13> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_14> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_15> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_16> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_17> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_18> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_19> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_20> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_21> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_22> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_23> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_24> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_25> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_26> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_27> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_28> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_29> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_30> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_31> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rvalidm1_tmp> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ARID_s_3> (without init value) has a constant value of 0 in block <KSPI_AXI>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <status_1> has a constant value of 0 in block <KSPI_SPI>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <status_7> has a constant value of 0 in block <KSPI_SPI>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_19> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_20> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_21> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_22> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_23> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_24> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_25> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_26> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_27> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_28> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_29> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_30> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_31> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rvalidm1_tmp> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bl_arreadym2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ust_rready> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rising_rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ARID_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_4> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_5> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_6> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_14> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_15> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_16> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_17> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_18> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_19> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_20> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_21> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_22> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_23> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_24> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_25> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_26> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_27> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_28> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_29> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_30> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_31> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rvalidm1_tmp> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bl_arreadym2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ust_rready> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rising_rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <id_in_3> (without init value) has a constant value of 0 in block <K_QDR_RAM1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <id_in_3> (without init value) has a constant value of 0 in block <K_QDR_RAM2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <id_in_3> (without init value) has a constant value of 0 in block <K_QDR_RAM3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <id_in_3> (without init value) has a constant value of 0 in block <K_QDR_RAM4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bl_arreadym2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ust_rready> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rising_rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ARID_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_4> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_5> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_6> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_7> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_8> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_9> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_10> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_11> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_12> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_13> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_17> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_18> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_19> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_20> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_21> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_22> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_23> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_24> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_25> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_26> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_27> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_28> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_29> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_30> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_31> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rvalidm1_tmp> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <awaddrm2_d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <bl_arreadym2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ust_rready> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rising_rreadym1_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <araddrm2_d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ARID_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_4> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_5> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_2> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_6> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_7> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_8> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_9> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_10> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_11> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ARID_3> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_16> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_15> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_14> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_13> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RDATAm1_12> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <RID_3> (without init value) has a constant value of 0 in block <K_QDR_RAM2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <RID_3> (without init value) has a constant value of 0 in block <K_QDR_RAM4>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rvalidm1_tmp_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <RID_3> (without init value) has a constant value of 0 in block <K_QDR_RAM3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RID_3> has a constant value of 0 in block <KSPI_AXI>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <RID_3> (without init value) has a constant value of 0 in block <K_QDR_RAM1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rvalidm1_tmp_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rvalidm1_tmp_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rvalidm1_tmp_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_0> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_1> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <araddrm2_2d_0> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <awaddrm2_2d_1> (without init value) has a constant value of 0 in block <write_ch>. This FF/Latch will be trimmed during the optimization process.
CODE
WARNING:Xst:2677 - Node <rg8d_0> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg8d_1> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg8d_2> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg8d_3> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg8d_4> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg8d_5> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg8d_6> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_0> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_1> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_2> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_3> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_4> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_5> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <rg_com_6> of sequential type is unconnected in block <M2_ETH>.
WARNING:Xst:2677 - Node <awaddrs_tmp_0> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_1> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_23> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_24> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_25> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_0> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_1> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_23> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_24> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_25> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_0> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_1> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_23> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_24> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_25> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_0> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_1> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_23> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_24> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_25> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_0> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_1> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_23> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_24> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_25> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_0> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_1> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_23> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_24> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_25> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_0> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_1> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_23> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_24> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_25> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_0> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_1> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_23> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_24> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_25> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_0> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_1> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_6> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_7> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_8> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_9> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_10> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_11> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_12> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_13> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_14> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_15> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_16> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_17> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_18> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_19> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_20> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_21> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_22> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_24> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <awaddrs_tmp_25> of sequential type is unconnected in block <write_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_0> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_1> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_6> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_7> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_8> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_9> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_10> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_11> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_12> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_13> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_14> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_15> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_16> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_17> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_18> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_19> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_20> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_21> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_22> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_24> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <araddrs_tmp_25> of sequential type is unconnected in block <read_ch>.
WARNING:Xst:2677 - Node <RG_com_isp_0> of sequential type is unconnected in block <KSPI_SPI>.
WARNING:Xst:2677 - Node <RG_com_isp_1> of sequential type is unconnected in block <KSPI_SPI>.
WARNING:Xst:2677 - Node <RG_com_isp_2> of sequential type is unconnected in block <KSPI_SPI>.
WARNING:Xst:1710 - FF/Latch <rvalidm1_tmp_d> (without init value) has a constant value of 0 in block <read_ch>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <rready_tmp> of sequential type is unconnected in block <BU_BUS>.
WARNING:Xst:2404 - FFs/Latches <AWID<3:3>> (without init value) have a constant value of 0 in block <write_channel>.
WARNING:Xst:2404 - FFs/Latches <ARID<3:3>> (without init value) have a constant value of 0 in block <read_channel>.
Synthesizing (advanced) Unit <Block_SPI_2LINE>.
The following registers are absorbed into counter <count_t>: 1 register on signal <count_t>.
Unit <Block_SPI_2LINE> synthesized (advanced).
Synthesizing (advanced) Unit <CC10CLED>.
The following registers are absorbed into counter <COUNT>: 1 register on signal <COUNT>.
Unit <CC10CLED> synthesized (advanced).
Synthesizing (advanced) Unit <CC22CLED>.
The following registers are absorbed into counter <COUNT>: 1 register on signal <COUNT>.
Unit <CC22CLED> synthesized (advanced).
Synthesizing (advanced) Unit <CT_AK>.
The following registers are absorbed into counter <tmp>: 1 register on signal <tmp>.
Unit <CT_AK> synthesized (advanced).
Synthesizing (advanced) Unit <ETH_WRITE>.
The following registers are absorbed into counter <ct_stack>: 1 register on signal <ct_stack>.
Unit <ETH_WRITE> synthesized (advanced).
Synthesizing (advanced) Unit <PPK>.
INFO:Xst:3231 - The small RAM <Mram_tmp> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 16-word x 64-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <A> | |
| diA | connected to signal <GND> | |
| doA | connected to signal <tmp> | |
-----------------------------------------------------------------------
Unit <PPK> synthesized (advanced).
Synthesizing (advanced) Unit <RAMB_1Kx32>.
INFO:Xst:3226 - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOA> <DOB>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1024-word x 32-bit | |
| mode | write-first | |
| clkA | connected to signal <CLKA> | rise |
| enA | connected to signal <ENA> | high |
| weA | connected to signal <WEA> | high |
| addrA | connected to signal <ADDRA> | |
| diA | connected to signal <DIA> | |
| doA | connected to signal <DOA> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 1024-word x 32-bit | |
| mode | write-first | |
| clkB | connected to signal <CLKB> | rise |
| enB | connected to signal <ENB> | high |
| weB | connected to signal <WEB> | high |
| addrB | connected to signal <ADDRB> | |
| diB | connected to signal <DIB> | |
| doB | connected to signal <DOB> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
Unit <RAMB_1Kx32> synthesized (advanced).
Synthesizing (advanced) Unit <RAMB_1Kx64>.
INFO:Xst:3226 - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <DOA> <DOB>
-----------------------------------------------------------------------
| ram_type | Block | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 1024-word x 64-bit | |
| mode | write-first | |
| clkA | connected to signal <CLKA> | rise |
| enA | connected to signal <ENA> | high |
| weA | connected to signal <WEA> | high |
| addrA | connected to signal <ADDRA> | |
| diA | connected to signal <DIA> | |
| doA | connected to signal <DOA> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
| Port B |
| aspect ratio | 1024-word x 64-bit | |
| mode | write-first | |
| clkB | connected to signal <CLKB> | rise |
| enB | connected to signal <ENB> | high |
| weB | connected to signal <WEB> | high |
| addrB | connected to signal <ADDRB> | |
| diB | connected to signal <DIB> | |
| doB | connected to signal <DOB> | |
-----------------------------------------------------------------------
| optimization | speed | |
-----------------------------------------------------------------------
CODE
Unit <RAMB_1Kx64> synthesized (advanced).
WARNING:Xst:2677 - Node <rg8d_0> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg8d_1> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg8d_2> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg8d_3> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg8d_4> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg8d_5> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg8d_6> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_0> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_1> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_2> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_3> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_4> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_5> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <rg_com_6> of sequential type is unconnected in block <ETH_WRITE>.
WARNING:Xst:2677 - Node <RG_com_isp_0> of sequential type is unconnected in block <Block_SPI_2LINE>.
WARNING:Xst:2677 - Node <RG_com_isp_1> of sequential type is unconnected in block <Block_SPI_2LINE>.
WARNING:Xst:2677 - Node <RG_com_isp_2> of sequential type is unconnected in block <Block_SPI_2LINE>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 3
1024x32-bit dual-port block RAM : 1
1024x64-bit dual-port block RAM : 1
16x64-bit single-port distributed Read Only RAM : 1
# Adders/Subtractors : 7
11-bit subtractor : 1
16-bit subtractor : 1
24-bit subtractor : 2
32-bit adder : 1
5-bit subtractor : 2
# Counters : 7
10-bit up counter : 1
10-bit updown counter : 3
22-bit updown counter : 1
4-bit up counter : 2
# Registers : 8524
Flip-Flops : 8524
# Comparators : 30
6-bit comparator equal : 30
# Multiplexers : 2794
1-bit 2-to-1 multiplexer : 1479
1-bit 4-to-1 multiplexer : 1
10-bit 2-to-1 multiplexer : 2
16-bit 2-to-1 multiplexer : 6
2-bit 2-to-1 multiplexer : 1
21-bit 2-to-1 multiplexer : 8
24-bit 2-to-1 multiplexer : 4
26-bit 2-to-1 multiplexer : 40
3-bit 2-to-1 multiplexer : 45
32-bit 2-to-1 multiplexer : 115
32-bit 32-to-1 multiplexer : 1
35-bit 4-to-1 multiplexer : 1
47-bit 4-to-1 multiplexer : 1
5-bit 2-to-1 multiplexer : 1079
7-bit 2-to-1 multiplexer : 8
8-bit 2-to-1 multiplexer : 3
# Xors : 45
1-bit xor2 : 45
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1710 - FF/Latch <bl_arreadym2> (without init value) has a constant value of 0 in block <read_channel>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bl_arreadym3> (without init value) has a constant value of 0 in block <read_channel>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ust_rready> (without init value) has a constant value of 0 in block <read_channel>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <RRESP_0> (without init value) has a constant value of 0 in block <Block_AMBA_AXI_slave>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <BRESP_0> (without init value) has a constant value of 0 in block <Block_AMBA_AXI_slave>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <status_1> has a constant value of 0 in block <Block_SPI_2LINE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <status_7> has a constant value of 0 in block <Block_SPI_2LINE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Q_34> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_35> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_36> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_37> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_38> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_39> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_40> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_41> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_42> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_43> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_44> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_45> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_46> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_47> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_48> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_49> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_50> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_51> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_52> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_53> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_54> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_55> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_56> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_57> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_58> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_59> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_60> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_61> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_62> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_63> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_0> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_1> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_2> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_3> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_4> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_5> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_6> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_7> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_8> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_9> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_10> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_11> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_12> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_13> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_14> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_15> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_16> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_17> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_18> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_19> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_20> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_21> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_22> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_23> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_27> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_28> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_29> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_30> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_31> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_32> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <Q_33> (without init value) has a constant value of 0 in block <PPK>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:1901 - Instance buf_cq in unit Kontr_QDR_OU_AXI of type BUFIO has been replaced by BUFIODQS
INFO:Xst:1901 - Instance buf_cq_inv in unit Kontr_QDR_OU_AXI of type BUFIO has been replaced by BUFIODQS
INFO:Xst:1901 - Instance XLXI_38 in unit SNK_OU of type MMCM_BASE has been replaced by MMCM_ADV
Optimizing unit <RG_D1> ...
Optimizing unit <ALU_I_v6_MUSER_BUSok> ...
Optimizing unit <SNK_OU> ...
Optimizing unit <LVDS_block> ...
Optimizing unit <Kontr_QDR_OU_AXI> ...
Optimizing unit <ETH_WRITE> ...
Optimizing unit <BUF_block> ...
Optimizing unit <write_channel> ...
Optimizing unit <read_channel> ...
Optimizing unit <Block_AMBA_AXI_slave> ...
Optimizing unit <Block_SPI_2LINE> ...
Optimizing unit <BUSok> ...
Optimizing unit <BU_BUSok> ...
Optimizing unit <ct_n> ...
Optimizing unit <RG_D2> ...
Optimizing unit <M2_1_HXILINX_BUSok> ...
Optimizing unit <shifter_i> ...