void port_init(void)
{

DDRA = 0xFF; PORTA = 0x80; //
DDRB = 0x19; PORTB = 0x0F; //
DDRC = 0xFF; PORTC = 0x00; //
DDRD = 0x08; PORTD = 0x64; //
DDRE = 0x06; PORTE = 0x03; //
DDRF = 0x00; PORTF = 0x00; //
DDRG = 0x03; PORTG = 0x00; //
DDRH = 0x00; PORTH = 0x80; //
DDRJ = 0x00; PORTJ = 0x00; //
DDRK = 0x00; PORTK = 0x00; //
DDRL = 0x00; PORTL = 0x04; //
}





void init_timer0(void) // íàñòðîéêà òàéìåðà0
{
TCCR0A = 0x00; //stop
TCCR0B = 0x00; //stop
TCNT0 = 0x00; // set count Timer/Counter
OCR0A = 250; // Output Compare Register A
TCCR0A = 0x00;
TCCR0B = 0x02;
TIMSK0 = 0x02; //
}

//èíèöèàëèçàöèÿ êîììóíèêàöèîííîãî ïîðòà 0
void uart0_init(void)
{
UCSR0A = 0x00;
UCSR0B = 0x00;
UCSR0C = 0x00;
UBRR0L = 12; // 38400
UBRR0H = 0;
UCSR0A = 0x00;
UCSR0B = 0xD8; //
UCSR0C = 0xAE; //

}



void uart1_init(void)
{
UCSR1A = 0x00;
UCSR1B = 0x00;
UCSR1C = 0x00;
//* for 115200
UBRR1L = 3;
UBRR1H = 0;
UCSR1A = 0x00;//0x00;
UCSR1B = 0xD8;
UCSR1C = 0xA6;

}


void init_peripheral(void)
{
disable_interrupt();

port_init();
init_timer0();
uart0_init();
uart1_init();
MCUCR = (1<<IVCE);
MCUCR = (1<<IVSEL);
XMCRA = 0x00;
XMCRB = 0x07;
EIMSK = 0x00;
EICRA = 0x00;
EICRB = 0x00;
//all peripherals are now initialised

enable_interrupt(); //start errant interrupts
}

void m_adcsetup(void)
{
ADCSRA = 0x00;// ñáðîñ íàñòðîåê ÀÖÏ
ADMUX = 0x00;// íàñòðîéêà êàíàëà ÀÖÏ
ADCSRA = 0xDE;// íàñòðîéêà ÀÖÏ
ADCSRB = 0x00;// äîïîëíèòåëüíàÿ íàñòðîéêà ÀÖÏ
DIDR0 = 0x00;
DIDR1 = 0x00;
}
void m_uart0setup(void)
{
UCSR0B = 0x00; //çàïðåò íà ïåðèîä èíèöèàëèçàöèè

UBRR0L = 12; //óñòàíîâèòü ñêîðîñòü ñâÿçè

UBRR0H = 0;

UCSR0A = 0x00; // óïðàâëÿþùèé ðåãèñòð À

#ifdef DEBUG_CONSOLE
UCSR0B = 0x18; // óïðàâëÿþùèé ðåãèñòð B
#else
UCSR0B = 0xD8; // óïðàâëÿþùèé ðåãèñòð B
#endif
UCSR0C = 0xAE; // óïðàâëÿþùèé ðåãèñòð C

}
void m_uart1setup(void)
{

UCSR1B = 0x00; //çàïðåò íà ïåðèîä èíèöèàëèçàöèè
UBRR1L = 3;
UBRR1H = 0;
UCSR1A = 0x00; // óïðàâëÿþùèé ðåãèñòð À
UCSR1B = 0xD8; // óïðàâëÿþùèé ðåãèñòð B
UCSR1C = 0xA6; // óïðàâëÿþùèé ðåãèñòð C
}

void m_portsetup(void)
{
DDRA = 0xFF;
PORTA = 0x00;
PORTB = 0x0F;//
DDRB = 0x19;
PORTC = 0x00; // óïðàâëåíèå íàïðÿæåíèåì ÏÍ
DDRC = 0xFF; // // óïðàâëåíèå íàïðÿæåíèåì ÏÍ
PORTD = 0x64; // òåðìîìåòð, äàò÷èê ñêâ. òîêà, ôîðñèðîâêà
DDRD = 0x08;
PORTE = 0x03;
DDRE = 0x06;
PORTF = 0x00; // 8 êàíàëîâ ÀÖÏ 0...7
DDRF = 0x00;
PORTG = 0x00; // îòêëþ÷åí
DDRG = 0x03;
PORTH = 0x80; // 1 âåíòèëÿòîð
DDRH = 0x00;
PORTJ = 0x00; // îòêëþ÷åí
DDRJ = 0x00;
PORTK = 0x00; // 8 êàíàëîâ ÀÖÏ 8...15
DDRK = 0x00;
PORTL = 0x04; // îòêëþ÷åí
DDRL = 0x00;



}

void m_timer0setup(void)
{
TCCR0A = 0x00; //Ñòîï
TCCR0B = 0x00; //Ñòîï
TCNT0 = 0x00; // Ñáðîñ
OCR0A = 125; // Çàõâàò
TCCR0A = 0x00; //ðåæèì ðàáîòû òàéìåðà - âíóòðåííåå òàêòèðîâàíèå (Fêâàðöà/8)
TCCR0B = 0x02; //ðåæèì ðàáîòû òàéìåðà - âíóòðåííåå òàêòèðîâàíèå (Fêâàðöà/64) è ñòàðò ñ÷åò÷èêà
TIMSK0 = 0x02;// ðàçðåøåíèå ïðåðûâàíèé ïî òàéìåðó 0

}
void m_timer1setup(void)
{
TCNT1H = 0x00; // ñáðîñ
TCNT1L = 0x00; // ñáðîñ
OCR1AH = 0x00; // ñáðîñ
OCR1AL = 0x00; // ñáðîñ
OCR1BH = 0x00; // ñáðîñ
OCR1BL = 0x00; // ñáðîñ
TCCR1A = 0x00; // ðåãèñòð óïðàâëåíèÿ À
TCCR1B = 0x06; // ðåãèñòð óïðàâëåíèÿ Â
TCCR1C = 0x00; // ðåãèñòð óïðàâëåíèÿ C
TIMSK1 = 0x00;// ïðåðûâàíèÿ ïî 1 Ò/Ñ âñå çàïðåùåíû
}

void m_timer3setup(void)
{
TCNT3H = 0x00; // ñáðîñ
TCNT3L = 0x00; // ñáðîñ
OCR3A = 0x8;
OCR3BH = 0x00; // ñáðîñ
OCR3BL = 0x00; // ñáðîñ
TCCR3A = 0x00; // ðåãèñòð óïðàâëåíèÿ À
TCCR3B = 0x03; // ðåãèñòð óïðàâëåíèÿ Â
TCCR3C = 0x02; // ðåãèñòð óïðàâëåíèÿ C
TIMSK3 = 0x00;
}

void m_timer4setup(void)
{
//
TCNT4H = 0x00; // ñáðîñ
TCNT4L = 0x00; // ñáðîñ
OCR4AH = 0x00; // ñáðîñ
OCR4AL = 0x00; // ñáðîñ
OCR4BH = 0x00; // ñáðîñ
OCR4BL = 0x00; // ñáðîñ
TCCR4A = 0x00; // ðåãèñòð óïðàâëåíèÿ À

TCCR4B = 0x06; // ðåãèñòð óïðàâëåíèÿ Â

TCCR4C = 0x00; // ðåãèñòð óïðàâëåíèÿ C

TIMSK4 = 0x00;// ïðåðûâàíèÿ ïî 4 Ò/Ñ âñå çàïðåùåíû
}

void m_timer5setup(void)
{
//
TCNT5H = 0x00; //
TCNT5L = 0x00; //
OCR5AH = 0x00; //
OCR5AL = 0x00; //
OCR5BH = 0x00; //
OCR5BL = 0x00; //
TCCR5A = 0x00; //
TCCR5B = 0x06; //
TCCR5C = 0x00; //
TIMSK5 = 0x00;//
}

int __low_level_init(void)
{
_CLI();
m_portsetup(); // íàñòðîéêà ïîðòîâ ÌÊ
m_adcsetup(); // íàñòðîéêà ÀÖÏ
m_uart0setup(); // íàñòðîéêà óàðòà 0
m_timer0setup(); // íàñòðîéêà òàéìåðà 0
m_timer1setup(); // íàñòðîéêà òàéìåðà 1
m_timer3setup(); // íàñòðîéêà òàéìåðà 3
m_timer4setup(); // íàñòðîéêà òàéìåðà 4
m_timer5setup(); // íàñòðîéêà òàéìåðà 5
MCUCR = (1<<IVCE);
MCUCR = 0x80;



XMCRB = 0x07;//À ðåãèñòð óïðàâëåíèÿ ïàìÿòüþ
EIMSK = 0x00;

EICRA = 0x00;
_SEI();
return 1;
}

BOOTRESET: ; Bootloader reset point!
;---- STACK INIT --------;
ldi tmp, low(ramend) ;
out SPL,tmp ;
ldi tmp,high(ramend) ;
out SPH,tmp ;
cli
;---- Move_interrupts ---;
in tmp,MCUCR ; Get MCUCR
mov tmp1,tmp ;
ori tmp,(1<<IVCE) ; Enable change of Interrupt Vectors
out MCUCR,tmp ;
ori tmp1,(1<<IVSEL) ; Move interrupts to Boot Flash section
out MCUCR,tmp1 ;




JMP RESET ; переход к основной программе.

RESET: ;
;---- STACK INIT ------;
ldi tmp, low(ramend) ;
out SPL,tmp ;
ldi tmp,high(ramend) ;
out SPH,tmp ;
;----------------------;
clr zero ;
clr loop2 ;
;--- Move_interrupts --;
in tmp,MCUCR ; Get MCUCR
ori tmp,(1<<IVCE) ; Enable change of Interrupt Vectors
out MCUCR,tmp ;
out MCUCR,zero ;
;----------------------;
sts WDTCR,zero ; disable watchdog Timer
sei ; enable interrupts