after 1 ns;

architecture RTL of testing
    signal shreg : std_logic_vector(2 downto 0) := (others => '0'); -- вот тут задаем начальное значние !
begin

library ieee;
use ieee.std_logic_1164.all;

entity reg_aclr is
port
(
clk : in std_logic;
aclr : in std_logic;
D : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end entity;

architecture RTL of reg_aclr is
signal shreg: std_logic_vector(3 downto 0) := (others => '0');
begin
process(aclr, clk)
begin
if (aclr = '1') then
shreg <= (others => '0');
elsif (rising_edge(clk)) then
shreg <= shreg(2 downto 0) & (D or shreg(3));
end if;
end process;
Q <= shreg;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity DFF_aclr is
port
(
clk : in std_logic;
aclr : in std_logic;
D : in std_logic;
Q : out std_logic := '0'
);
end entity;
architecture RTL of DFF_aclr is
begin
reg_proc : process(aclr, clk)
begin
if (aclr = '1') then
Q <= '0';
elsif (rising_edge(clk)) then
Q <= D;
end if;
end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity reg_aclr is
port
(
clk : in std_logic;
aclr : in std_logic;
D : in std_logic;
Q : out std_logic_vector(3 downto 0)
);
end entity;

architecture RTL of reg_aclr is
signal iQ: std_logic_vector(3 downto 0) := (others => '0');
begin
--===============================================
-- Первый триггер в цепочке сдвигового регистра
--===============================================
DFF0_aclr_comp : entity work.DFF_aclr
port map
(
clk => clk,
aclr => aclr,
D => D or iq(3),
Q => iQ(0)
);

--===============================================
-- Остальные триггера
--===============================================
reg_3to1generate : for i in 0 to 2 generate
DFF_aclr_comp : entity work.DFF_aclr
port map
(
clk => clk,
aclr => aclr,
D => iQ(i),
Q => iQ(i + 1)
);
end generate;
Q <= iQ;
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;

entity \3REG\ is
  port(
       CLKT : in STD_LOGIC;
       RS : in STD_LOGIC;
       RST : in STD_LOGIC;
       Q : out STD_LOGIC_VECTOR(0 to 3):= (others => '0')
  );
end \3REG\;

architecture \3REG\ of \3REG\ is

component \4DFF\
  port (
       CLK : in STD_LOGIC;
       D0,D1,D2,D3 : in STD_LOGIC;
       RS0,RS1,RS2,RS3 : in STD_LOGIC;
       Q0,Q1,Q2,Q3 : out STD_LOGIC
       );
end component;

signal D0 : STD_LOGIC;
signal QT0,QT1,QT2,QT3 : STD_LOGIC := '0';

begin
        
U10 : \4DFF\
  port map(
       CLK => CLKT,
       D0 => D0,
       D1 => QT0,
       D2 => QT1,
       D3 => QT2,
       Q0 => QT0,
       Q1 => QT1,
       Q2 => QT2,
       Q3 => QT3,
       RS0 => RST,
       RS1 => RST,
       RS2 => RST,
       RS3 => RST
  );

Q(3) <= QT3;
Q(2) <= QT2;
Q(1) <= QT1;
Q(0) <= QT0;
D0 <= RS or QT3;

    
end \3REG\;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity \4DFF\ is
     port(
         D0,D1,D2,D3 : in STD_LOGIC;
         CLK : in STD_LOGIC;
         RS0,RS1,RS2,RS3 : in STD_LOGIC;
         Q0,Q1,Q2,Q3 : out STD_LOGIC := '0'
           );
end \4DFF\;

architecture \4DFF\ of \4DFF\ is
begin
    
process( CLK,RS0,RS1,RS2,RS3 )
   begin  
             
     if ( RS0='1') then    Q0 <= '0';
     elsif ( rising_edge (CLK)) then Q0 <= D0;
     end if;    
    
     if ( RS1='1') then    Q1 <= '0';
     elsif ( rising_edge (CLK)) then Q1 <= D1;
     end if;    
      
     if ( RS2='1') then    Q2 <= '0';
     elsif ( rising_edge (CLK)) then Q2 <= D2;
     end if;    
    
     if ( RS3='1') then    Q3 <= '0';
     elsif ( rising_edge (CLK) ) then Q3 <= D3;
     end if;    
    end process;    
    
end \4DFF\;

library ieee;
use ieee.std_logic_1164.all;

entity DFF_aclr is
port
(
D0,D1,D2,D3 : in STD_LOGIC;
CLK : in STD_LOGIC;
RS0,RS1,RS2,RS3 : in STD_LOGIC;
Q0,Q1,Q2,Q3 : out STD_LOGIC := '0'
);
end DFF_aclr;

architecture DFF_aclr of DFF_aclr is
begin

process
(
CLK,
RS0,
RS1,
RS2,
RS3
)
begin
if (RS0='1') then
Q0 <= '0';
elsif (rising_edge (CLK)) then
Q0 <= D0;
end if;

if (RS1='1') then
Q1 <= '0';
elsif (rising_edge (CLK)) then
Q1 <= D1;
end if;

if (RS2='1') then
Q2 <= '0';
elsif (rising_edge (CLK)) then
Q2 <= D2;
end if;

if (RS3='1') then
Q3 <= '0';
elsif (rising_edge (CLK)) then
Q3 <= D3;
end if;
end process;
end DFF_aclr;

library IEEE;
use IEEE.std_logic_1164.all;
entity reg_aclr is
port(
CLKT : in STD_LOGIC;
RS : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(0 to 3):= (others => '0')
);
end reg_aclr;

architecture reg_aclr of reg_aclr is

component DFF_aclr
port (
CLK : in STD_LOGIC;
D0,D1,D2,D3 : in STD_LOGIC;
RS0,RS1,RS2,RS3 : in STD_LOGIC;
Q0,Q1,Q2,Q3 : out STD_LOGIC
);
end component;

signal D0 : STD_LOGIC;
signal QT0,QT1,QT2,QT3 : STD_LOGIC := '0';

begin

U10 : DFF_aclr
port map(
CLK => CLKT,
D0 => D0,
D1 => QT0,
D2 => QT1,
D3 => QT2,
Q0 => QT0,
Q1 => QT1,
Q2 => QT2,
Q3 => QT3,
RS0 => RST,
RS1 => RST,
RS2 => RST,
RS3 => RST
);

Q(3) <= QT3;
Q(2) <= QT2;
Q(1) <= QT1;
Q(0) <= QT0;
D0 <= RS or QT3;
end reg_aclr;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY reg_aclr_vhd_tst IS
END reg_aclr_vhd_tst;
ARCHITECTURE reg_aclr_arch OF reg_aclr_vhd_tst IS
-- constants
-- signals
SIGNAL CLKT : STD_LOGIC;
SIGNAL Q : STD_LOGIC_VECTOR(0 TO 3);
SIGNAL RS : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
COMPONENT reg_aclr
PORT (
CLKT : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(0 TO 3);
RS : IN STD_LOGIC;
RST : IN STD_LOGIC
);
END COMPONENT;
--▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓
--========================================================================
-- Формирование констант для вычисления периодв CLK от частоты работы
--========================================================================
constant clk_freq : real := 100.0; -- MHz
constant clk_prd : time := (1000.0/clk_freq) * 1.0 ns; -- Вычисление периода CLK
BEGIN
i1 : reg_aclr
PORT MAP (
-- list connections between master ports and signals
CLKT => CLKT,
Q => Q,
RS => RS,
RST => RST
);
--==========================================
-- Задание тактовой частоты проекта
--==========================================
process
begin
CLKT <= '0'; wait for clk_prd/2;
CLKT <= '1'; wait for clk_prd/2;
end process;

process
begin
wait for 15*clk_prd;
RS <= '1';
wait for clk_prd;
RS <= '0';
wait;
end process;

process
begin
wait for 50*clk_prd;

RST <= '1';
wait for 3*clk_prd;
RST <= '0';
wait;
end process;

END reg_aclr_arch;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity REG30 is
     port(
         CLKR : in STD_LOGIC;
         RS0 : in STD_LOGIC;
         RST : in STD_LOGIC;
         Q : out STD_LOGIC_VECTOR(0 to 3) := (others => '0')
         );
end REG30;

architecture RTL of REG30 is
component DFF4
  port (
       CLK : in STD_LOGIC;
       D0,D1,D2,D3 : in STD_LOGIC;
       RS0,RS1,RS2,RS3 : in STD_LOGIC;
       Q0,Q1,Q2,Q3 : out STD_LOGIC
       );
end component;

signal D0 : STD_LOGIC;
signal QT0,QT1,QT2,QT3 : STD_LOGIC := '0';

begin

U1 : DFF4
  port map(
       CLK => CLKR,
       D0 => D0,
       D1 => QT0,
       D2 => QT1,
       D3 => QT2,
       Q0 => QT0,
       Q1 => QT1,
       Q2 => QT2,
       Q3 => QT3,
       RS0 => RS0,
       RS1 => RS0,
       RS2 => RS0,
       RS3 => RS0
  );

    Q(3) <= QT3;
    Q(2) <= QT2;
    Q(1) <= QT1;
    Q(0) <= QT0;
    D0 <= RST or QT3;

end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity DFF4 is
     port(
         D0,D1,D2,D3 : in STD_LOGIC;
         CLK : in STD_LOGIC;
         RS0,RS1,RS2,RS3 : in STD_LOGIC;
         Q0,Q1,Q2,Q3 : out STD_LOGIC := '0'
           );
end DFF4;

architecture RTL of DFF4 is
begin
    
process( CLK,RS0,RS1,RS2,RS3 )
   begin  
             
     if ( RS0='1') then    Q0 <= '0';
     elsif ( rising_edge (CLK)) then Q0 <= D0;
     end if;    
    
     if ( RS1='1') then    Q1 <= '0';
     elsif ( rising_edge (CLK)) then Q1 <= D1;
     end if;    
      
     if ( RS2='1') then    Q2 <= '0';
     elsif ( rising_edge (CLK)) then Q2 <= D2;
     end if;    
    
     if ( RS3='1') then    Q3 <= '0';
     elsif ( rising_edge (CLK) ) then Q3 <= D3;
     end if;    
    end process;    
end architecture;