Код
module count (input clk, output reg [1:0]counter);
always @(posedge clk)
counter <= counter + 1;
endmodule
always @(posedge clk)
counter <= counter + 1;
endmodule
Test bench
Код
module top;
reg clk;
wire [1:0] counter;
count tcount (clk, counter);
initial
begin
clk = 0;
forever #10 clk = !clk;
end
endmodule
reg clk;
wire [1:0] counter;
count tcount (clk, counter);
initial
begin
clk = 0;
forever #10 clk = !clk;
end
endmodule
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