alt_sgdma_descriptor *desc = (alt_sgdma_descriptor *) ONCHIP_MEMORY2_1_BASE;
alt_sgdma_descriptor *currdescriptor_ptr;

currdescriptor_ptr =  &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST];

currdescriptor_ptr =  desc+ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST;

currdescriptor_ptr =  desc+sizeof(alt_sgdma_descriptor)*ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST;

void TseMacSgDmaReadInit()
{
    alt_u32 *uncached_packet_payload;
    uncached_packet_payload = (void *)alt_remap_cached ((volatile void*) rx_pkt, 4);
    
    currdescriptor_ptr =  &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST];
    nextdescriptor_ptr = (alt_sgdma_descriptor *) IORD_ALTERA_TSE_SGDMA_DESC_NEXT(currdescriptor_ptr);
    blockdescriptor_ptr = currdescriptor_ptr;
    alt_avalon_sgdma_construct_stream_to_mem_desc(
            (alt_sgdma_descriptor *) &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST],  // descriptor I want to work with
            (alt_sgdma_descriptor *) &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST],  // pointer to "next"
            uncached_packet_payload,            // pkt_array[chain_loop]->nb_buff,                     // starting write_address
            0,                                  // read until EOP
            0);
  
    currdescriptor_ptr =  &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST];
    nextdescriptor_ptr = (alt_sgdma_descriptor *) IORD_ALTERA_TSE_SGDMA_DESC_NEXT(currdescriptor_ptr);
    
    int desc_status = 1;
    desc_status = alt_avalon_sgdma_check_descriptor_status(currdescriptor_ptr);
    desc_status = alt_avalon_sgdma_check_descriptor_status(nextdescriptor_ptr);  
    desc_pointer = currdescriptor_ptr;
    
    TseMacRxRead(currdescriptor_ptr);
    
    alt_u32 sgdma_control_rx = 0;
    sgdma_control_rx = IORD_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_1_BASE);
    alt_u32 sgdma_status_rx = 0;
    sgdma_status_rx = IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_1_BASE);
}

int TseMacReceive(){
    alt_u32 *uncached_packet_payload;
    alt_u8 tempVar;
    desc_pointer = currdescriptor_ptr;
    alt_u32 desc_stat=0;
    desc_stat = IORD_ALTERA_TSE_SGDMA_DESC_STATUS(desc_pointer);
    
    if ((desc_stat & ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) )
    {
        desc_pointer->status&=~ALTERA_AVALON_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK;
        nextdescriptor_ptr = (alt_sgdma_descriptor *)IORD_ALTERA_TSE_SGDMA_DESC_NEXT(desc_pointer);
    
        uncached_packet_payload = (void *)alt_remap_cached ((volatile void*) rx_pkt, 4);
       tempVar = IORD_8DIRECT(&nextdescriptor_ptr->control, 0 );
    
        alt_avalon_sgdma_construct_stream_to_mem_desc(
            (alt_sgdma_descriptor *) &desc[ALTERA_TSE_FIRST_RX_SGDMA_DESC_OFST],  // descriptor I want to work with
            (alt_sgdma_descriptor *) &desc[ALTERA_TSE_SECOND_RX_SGDMA_DESC_OFST],  // pointer to "next"
            uncached_packet_payload,            // starting write_address
            0,                                  // read until EOP
            0);                                 // don't write to constant address
        
        IOWR_8DIRECT(&nextdescriptor_ptr->control, 0, tempVar);
        
      //  desc_pointer = nextdescriptor_ptr;
            }
    return 1;
}

alt_u32  TseMacRxRead(alt_sgdma_descriptor *rxDesc)
{
    
    alt_u32 sgdma_status_rx = 0;
    sgdma_status_rx = IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_1_BASE);
    alt_u32 sgdma_control_rx = 0;
    sgdma_control_rx = IORD_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_1_BASE);
    
    alt_u8 result = 0;
    while ( (IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_1_BASE) & ALTERA_AVALON_SGDMA_STATUS_BUSY_MSK) ){
    }
    result = alt_avalon_sgdma_do_async_transfer(sgdma_rx_dev, (alt_sgdma_descriptor *) rxDesc /*&rxDesc[0]*/);
    

        
return 0;
}


int TseMacSgDmaRxIsr(void * context, alt_u32 id)
{
    alt_u32 rx_section = 0;
    rx_section = IORD_ALTERA_TSEMAC_RX_SECTION_EMPTY(sgdma_rx_dev);
    rx_section = IORD_ALTERA_TSEMAC_CMD_CONFIG(TRIPLE_SPEED_ETHERNET_0_BASE);
    
          //TseMacReceive();    
    IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_1_BASE, 0x00);
    IOWR_ALTERA_AVALON_SGDMA_CONTROL(SGDMA_1_BASE, ALTERA_TSE_SGDMA_INTR_MASK);

        
    if((IORD_ALTERA_AVALON_SGDMA_STATUS(SGDMA_1_BASE) & ALTERA_AVALON_SGDMA_STATUS_CHAIN_COMPLETED_MSK )){
       TseMacRxRead(currdescriptor_ptr/*desc*/);
    }    
    
    IOWR_ALTERA_AVALON_SGDMA_STATUS(SGDMA_1_BASE,0xFF);
    
       // тут у меня обработка принятого пакета  &rx_pkt[0]

     TseMacReceive();                
return 0;
}

#include <stdio.h>
#include <stdlib.h>
#include "sys/alt_dma.h"
#include "system.h"
static volatile int rx_done = 0;
/*
* Callback function that obtains notification that the data
* is received.
*/
static void done (void* handle, void* data)
{
    rx_done++;
}
/*
*
*/
int main (int argc, char* argv[], char* envp[])
{
    int rc;
    alt_dma_txchan txchan;
    alt_dma_rxchan rxchan;
    void* tx_data = (void*) 0x901000; /* pointer to data to send */
    void* rx_buffer = (void*) 0x902000; /* pointer to rx buffer */
    /* Create the transmit channel */
    if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL)
    {
        printf ("Failed to open transmit channel\n");
        exit (1);
    }
    /* Create the receive channel */
    if ((rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL)
    {
        printf ("Failed to open receive channel\n");
        exit (1);
    }
    /* Post the transmit request */
    if ((rc = alt_dma_txchan_send (txchan,
        tx_data,
        128,
        NULL,
        NULL)) < 0)
    {
        printf ("Failed to post transmit request, reason = %i\n", rc);
        exit (1);
    }
...

    int psize = 528; // размер передаваемого массива
    alt_u8 *rx_buf;
    alt_u8 *tx_buf;
   int rc;
    
    

tx_buf = packet+34;  // указатель на место откуда
rx_buf = 34+pkt_pointer+offset; // указатель куда

     if ((rc = alt_dma_txchan_send ( txchan,
                                    tx_buf,
                                    psize,
                                        NULL,
                                        NULL)) < 0)
        {
        printf ("Failed to post transmit request, reason = %i\n", rc);
        exit (1);
        }
      
    if ((rc = alt_dma_rxchan_prepare (  rxchan,
                                       rx_buf,
                                       psize,
                                        done,
                                        NULL)) < 0)
        {
        printf ("Failed to post read request, reason = %i\n", rc); // вот тут вылетаем с кодом -22
        exit (1);
        }
        /* wait for transfer to complete */
        while (!rx_done);
                      #ifdef DEBUG_IP
                      printf ("DMA transfer successful!\n");
                      #endif

    void* tx_data = (void*) ...; /* pointer to data to send */
    void* rx_buffer = (void*) ...; /* pointer to rx buffer */

; Device                            ; EP2C8Q208C8                                  ;
; Total logic elements              ; 6,484 / 8,256 ( 79 % )                       ;
;     Total combinational functions ; 5,844 / 8,256 ( 71 % )                       ;
;     Dedicated logic registers     ; 4,199 / 8,256 ( 51 % )                       ;
; Total registers                   ; 4267                                         ;
; Total pins                        ; 127 / 138 ( 92 % )                           ;
; Total memory bits                 ; 50,944 / 165,888 ( 31 % )                    ;
; Embedded Multiplier 9-bit elements; 4 / 36 ( 11 % )                              ;
; Total PLLs                        ; 1 / 2 ( 50 % )                               ;

alt_u32 t2;
IOWR_ALTERA_TSEMAC_MDIO_ADDR0(TSE_MAC_BASE,PHY);
t2 = IORD_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,0x1B);//Extended PHY Specific Status Register
t2 &= 0xFFF0;
IOWR_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,0x1B,t2|0xB);//RGMII to Copper
t2 = IORD_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,0x14);//Extended PHY Specific Control Register
IOWR_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,0x14,t2|0x82);//Add Delay to RX_CLK for RXD Outputs; Add Delay to GTX_CLK for TXD Inputs
t2 = IORD_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,ALTERA_TSEMAC_PHY_ADDR_CONTROL);
IOWR_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,ALTERA_TSEMAC_PHY_ADDR_CONTROL,t2|PCS_CTL
_sw_reset);//Previous Operations Require SW Reset
do
{
t2 = IORD_ALTERA_TSEMAC_MDIO(TSE_MAC_BASE,0,ALTERA_TSEMAC_PHY_ADDR_STATUS);
}
while((t2&0x04)==0);//wait for link-up