library ieee;
use ieee.std_logic_1164.all;

entity async_sram_256kx32 is
port( ats_address        : in std_logic_vector(17 downto 0);
      ats_read_n         : in std_logic;
      ats_write_n        : in std_logic;
      ats_chipselect_n   : in std_logic;
      ats_byteenable_n   : in std_logic_vector(3 downto 0);
      ats_data           : inout std_logic_vector(31 downto 0);

      cos_addr           : out std_logic_vector(17 downto 0);
      cos_read_n         : out std_logic;
      cos_write_n        : out std_logic;
      cos_chipselect_n   : out std_logic;
      cos_byteenable_n   : out std_logic_vector(3 downto 0)
     );
end async_sram_256kx32;

architecture rtl of async_sram_256kx32 is

begin
  cos_addr <= ats_address;
  cos_read_n <= ats_read_n;
  cos_write_n <= ats_write_n;
  cos_chipselect_n <= ats_chipselect_n;
  cos_byteenable_n <= ats_byteenable_n;

end rtl;

module    SRAM
    (
    //    Host Data
    oDATA,iDATA,iADDR,
    iWE_N,iOE_N,
    iCE_N,iCLK,
    //    SRAM
    SRAM_DQ,
    SRAM_ADDR,
    SRAM_WE_N,
    SRAM_CE_N,
    SRAM_OE_N
    );
//    Host Side
input    [7:0]    iDATA;
output    [7:0]    oDATA;
input    [5:0]    iADDR;
input            iWE_N,iOE_N;
input            iCE_N,iCLK;

//    SRAM Side
inout    [7:0]    SRAM_DQ;
output    [5:0]    SRAM_ADDR;
output            SRAM_WE_N,
                SRAM_CE_N,
                SRAM_OE_N;

assign    SRAM_DQ     =    SRAM_WE_N ? 8'hzz : iDATA;
assign    oDATA        =    SRAM_DQ;
assign    SRAM_ADDR    =    iADDR;
assign    SRAM_WE_N    =    iWE_N;
assign    SRAM_OE_N    =    iOE_N;
assign    SRAM_CE_N    =    iCE_N;

endmodule

#include "system.h"
#include "altera_avalon_pio_regs.h"
#include "alt_types.h"

unsigned char* ptr_byte;
unsigned char a;

int main (void)
{    
     ptr_byte = (unsigned char*)SRAM_INST_BASE;
    while(1)
    {
    IOWR(VYHOD_BASE,0,1);  // использую для синхронизации оциллографа
            
    *ptr_byte = 0x55; //процесс записи

    IOWR(VYHOD_BASE,0,0);// использую для синхронизации оциллографа

    a = *ptr_byte; //процесс чтения

     };
return 0;
}

assign    SRAM_DQ     =    SRAM_WE_N ? 8'hzz : iDATA;