NET "clk"  LOC = "p181" | IOSTANDARD = LVCMOS33;

NET "FX2_FD[0]"  LOC = "p192" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[1]"  LOC = "p187" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[2]"  LOC = "p189" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[3]"  LOC = "p190" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[4]"  LOC = "p172" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[5]"  LOC = "p171" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[6]"  LOC = "p168" | IOSTANDARD = LVCMOS33;
NET "FX2_FD[7]"  LOC = "p167" | IOSTANDARD = LVCMOS33;
NET "FX2_flags[0]"  LOC = "p169" | IOSTANDARD = LVCMOS33;
NET "FX2_flags[1]"  LOC = "p174" | IOSTANDARD = LVCMOS33;
NET "FX2_flags[2]"  LOC = "p175" | IOSTANDARD = LVCMOS33;
NET "FX2_PA_2"  LOC = "p178" | IOSTANDARD = LVCMOS33;
NET "FX2_PA_3"  LOC = "p179" | IOSTANDARD = LVCMOS33;
NET "FX2_PA_4"  LOC = "p180" | IOSTANDARD = LVCMOS33;
NET "FX2_PA_5"  LOC = "p161" | IOSTANDARD = LVCMOS33;
NET "FX2_PA_6"  LOC = "p160" | IOSTANDARD = LVCMOS33;
NET "FX2_PA_7"  LOC = "p159" | IOSTANDARD = LVCMOS33;
NET "FX2_SLRD"  LOC = "p185" | IOSTANDARD = LVCMOS33;
NET "FX2_SLWR"  LOC = "p186" | IOSTANDARD = LVCMOS33;

NET "LED[0]"  LOC = "p146" | IOSTANDARD = LVCMOS33;
NET "LED[1]"  LOC = "p147" | IOSTANDARD = LVCMOS33;
NET "pushbutton"  LOC = "p148" | IOSTANDARD = LVCMOS33;

NET "RxD"  LOC = "p193" | IOSTANDARD = LVCMOS33;
NET "TxD"  LOC = "p196" | IOSTANDARD = LVCMOS33;

NET "Ethernet_RDp"  LOC = "p150" | IOSTANDARD = LVCMOS33;
NET "Ethernet_TDm"  LOC = "p152" | IOSTANDARD = LVCMOS33;
NET "Ethernet_TDp"  LOC = "p151" | IOSTANDARD = LVCMOS33;

DWORD USB_BulkRead(DWORD pipe, void* buffer, DWORD buffersize)
{
    DWORD nBytes;
    assert(buffersize<0x10000);
    DeviceIoControl(XyloDeviceHandle, 0x22204E, &pipe, sizeof(pipe), buffer, buffersize, &nBytes, NULL);
    return nBytes;
}

void TD_Init( void )
{ // Called once at startup

  SYNCDELAY;                    //
  REVCTL=0x03;

  SYNCDELAY;                    //
  CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation, output CLKOUT

  SYNCDELAY;                    //
  IFCONFIG = 0xCB; // for async

  SYNCDELAY;                    //
  PORTACFG = 0x40;  // FLAGD is /CHIPSELECT


  // EP2 512 BULK OUT 4x
  SYNCDELAY;                    // see TRM section 15.14
  EP2CFG = 0xA0;                // BUF[1:0]=00 for 4x buffering
  
  // EP6 512 BULK IN 4x
  SYNCDELAY;                    //
  EP6CFG = 0xE0;                // BUF[1:0]=00 for 4x buffering
  
  // EP4 and EP8 are not used in this implementation...
  SYNCDELAY;                    //
  EP4CFG = 0x20;                // clear valid bit
  SYNCDELAY;                    //
  EP8CFG = 0x60;                // clear valid bit


  SYNCDELAY;
  FIFORESET = 0x80;             // activate NAK-ALL to avoid race conditions
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x82;             // reset, FIFO 2
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x84;             // reset, FIFO 4
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x86;             // reset, FIFO 6
  SYNCDELAY;                    //
  FIFORESET = 0x88;             // reset, FIFO 8
  SYNCDELAY;                    // see TRM section 15.14
  FIFORESET = 0x00;             // deactivate NAK-ALL

  SYNCDELAY;                    //
  OUTPKTEND = 0x82;
  SYNCDELAY;                    //
  OUTPKTEND = 0x82;
  SYNCDELAY;                    //
  OUTPKTEND = 0x82;
  SYNCDELAY;                    //
  OUTPKTEND = 0x82;


  SYNCDELAY;                    //
  EP2FIFOCFG = 0x11;            // AUTOOUT=1, WORDWIDE=1
  
  SYNCDELAY;                    //
  EP6FIFOCFG = 0x0D;            // AUTOIN=1, WORDWIDE=1

  SYNCDELAY;
  EP6AUTOINLENH = 0x02;
  SYNCDELAY;
  EP6AUTOINLENL = 0x00;


  SYNCDELAY;
  PINFLAGSAB = 0xE0;            // FLAGA - indexed, FLAGB - EP6FF
  SYNCDELAY;
  PINFLAGSCD = 0x08;            // FLAGC - EP2EF, FLAGD - indexed
  SYNCDELAY;

  FIFOPINPOLAR = 0x00;
  SYNCDELAY;

}