library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity test is port
(
Clk:in std_logic;    --входной сигнал синхронизации 50 МГц
ClkOut:out std_logic; --выходной умноженный сигнал
CounterOut:out std_logic_vector(7 downto 0)
);
end test;

architecture test_arch of test is

signal c:std_logic; --сигнал на выходе умножителя

signal counter:std_logic_vector(7 downto 0):=(others => '0'); --счётчик

component pll port
(
inclk0:in std_logic:='0';
c0:out std_logic
);

end component;

begin

pll_inst:pll port map(Clk,c);

process(c)
begin
if rising_edge(c) then
  counter<=counter+1;
end if;
end process;

ClkOut<=counter(0); --ошибка

Counterout(0)<=counter(0); --нет ошибки

end test_arch;

process(Clk)
begin
if rising_edge(Clk) then
  if R_M(0)='0' then
   WriteAddress:=("101000000"*Y)+X;
  else
   WriteAddress:=("010100000"*Y)+X;
  end if;
end if;
end process;

process(Clk)
begin
if rising_edge(Clk) then
  CE<=Port_CE;
  WE<=Port_WE;
  A<=Port_A;
  D<=Port_D;
end if;
end process;

process(Clk)
variable W2:std_logic_vector(8 downto 0);
variable X0:std_logic_vector(8 downto 0);
variable X1:std_logic_vector(8 downto 0);
variable H2:std_logic_vector(7 downto 0);
variable Y0:std_logic_vector(7 downto 0);
variable Y1:std_logic_vector(7 downto 0);
begin
if rising_edge(Clk) then
  if State=0 then
   if (CE='0' and WE='1') then
    State:=1;
   end if;
  else
   if (CE='0' and WE='0') then
    State:=0;
    if A='0' then
     case D(15 downto 12) is
      when "1001" =>
       R_P:=D(0);
      when "1010" =>
       R_W:=D(8 downto 0);
       W2:='0'&R_W(8 downto 1);
       X0:="010100000"-W2;
       X1:="010011111"+W2;
       X:=X0;
      when "1011" =>
       R_H:=D(7 downto 0);
       H2:='0'&R_H(7 downto 1);
       Y0:="01111000"-H2;
       Y1:="01110111"+H2;
       Y:=Y0;
      when others =>null;
     end case;
    else
     if X=X1 then
      X:=X0;
      if Y=Y1 then
       Y:=Y0;
      else
       Y:=Y+1;
      end if;
     else
      X:=X+1;
     end if;
    end if;
   end if;
  end if;
end if;
end process;

VRAM0_CE<='0';
VRAM1_CE<='0';

VRAM0_OE<=H(0) when (R_P='0' and Blank='1') else '1';
VRAM1_OE<=H(0) when (R_P='1' and Blank='1') else '1';

process(Clk)
begin
if rising_edge(Clk) then
  if A='1' then
   if R_P='0' then
    VRAM0_WE<='1';
    VRAM1_WE<=WE;
   else
    VRAM0_WE<=WE;
    VRAM1_WE<='1';
   end if;
  else
   VRAM0_WE<='1';
   VRAM1_WE<='1';
  end if;
end if;
end process;

process(Clk)
begin
if rising_edge(Clk) then
  if R_P='0' then
   VRAM0_A<=ReadAddress;
   VRAM1_A<=WriteAddress;
   VRAM0_D<=(others => 'Z');
   VRAM1_D<=D;
  else
   VRAM0_A<=WriteAddress;
   VRAM1_A<=ReadAddress;
   VRAM0_D<=D;
   VRAM1_D<=(others => 'Z');
  end if;
end if;
end process;

process(C)
begin
if rising_edge(C) then
  CE1<=Port_CE;
  WE1<=Port_WE;
  A1<=Port_A;
  D1<=Port_D;
  CE2<=CE1;
  WE2<=WE1;
  A2<=A1;
  D2<=D1;
  if R_M(0)='0' then
   WriteAddress1<=("101000000"*Y)+X;
  else
   WriteAddress1<=("010100000"*Y)+X;
  end if;
  WriteAddress2<=WriteAddress1;
end if;
end process;

process(C)
variable W2:std_logic_vector(8 downto 0);
variable X0:std_logic_vector(8 downto 0);
variable X1:std_logic_vector(8 downto 0);
variable H2:std_logic_vector(7 downto 0);
variable Y0:std_logic_vector(7 downto 0);
variable Y1:std_logic_vector(7 downto 0);
begin
if rising_edge(C) then
  if(WE1='0' and WE2='1') then
   if CE2='0' then
    if A2='0' then
     case D2(15 downto 12) is
      when "1001" =>
       R_P:=D2(0);
      when "1010" =>
       R_W:=D2(8 downto 0);
       W2:='0'&R_W(8 downto 1);
       X0:="010100000"-W2;
       X1:="010011111"+W2;
       X:=X0;
      when "1011" =>
       R_H:=D2(7 downto 0);
       H2:='0'&R_H(7 downto 1);
       Y0:="01111000"-H2;
       Y1:="01110111"+H2;
       Y:=Y0;
      when others =>null;
     end case;
    else
     if X=X1 then
      X:=X0;
      if Y=Y1 then
       Y:=Y0;
      else
       Y:=Y+1;
      end if;
     else
      X:=X+1;
     end if;
    end if;
   end if;
  end if;
end if;
end process;

VRAM0_CE<='0';
VRAM1_CE<='0';

VRAM0_OE<=H(0) when (R_P='0' and Blank='1') else '1';
VRAM1_OE<=H(0) when (R_P='1' and Blank='1') else '1';

VRAM0_WE<=WE2 when (A2='1' and R_P='1') else '1';
VRAM1_WE<=WE2 when (A2='1' and R_P='0') else '1';

VRAM0_D<=D2 when R_P='1' else (others => 'Z');
VRAM1_D<=D2 when R_P='0' else (others => 'Z');

VRAM0_A<=WriteAddress2 when R_P='1' else ReadAddress;
VRAM1_A<=WriteAddress2 when R_P='0' else ReadAddress;

end VideoFlipper_Architecture;

module interck2 ( in, out, clka, clkb, reset, completed);
input in, clka,clkb,reset;
output out, completed;

reg in_at_clka;
reg [1:0] out_at_clkb;

wire clra = reset | out_at_clkb[1];

always @(posedge clka or posedge clra)
  if (clra) in_at_clka <= 1'b0;
  else if (in) in_at_clka <= 1'b1;

always @(posedge clkb or posedge reset)
  if (reset) out_at_clkb <= 2'b00;
  else out_at_clkb <= {out_at_clkb[0] & !out_at_clkb[1], in_at_clka};

assign out = out_at_clkb[1];

reg [1:0] cmpl_at_clka;
reg cmpl_at_clkb;
wire clrb = reset | cmpl_at_clka[1];

always @(posedge clkb or posedge clrb)
  if (clrb) cmpl_at_clkb <= 1'b0;
  else if (out_at_clkb[1]) cmpl_at_clkb <= 1'b1;

always @(posedge clka or posedge reset)
  if (reset) cmpl_at_clka <= 2'h0; else
  cmpl_at_clka <= {cmpl_at_clka[0] & !cmpl_at_clka[1], cmpl_at_clkb};

assign completed = cmpl_at_clka[1];

endmodule

      
when "1011" =>
       R_H:=D(7 downto 0);
       H2:='0'&R_H(7 downto 1);
       Y0:="01111000"-H2;
       Y1:="01110111"+H2;
       Y:=Y0;

when "1011" =>
       Y <="01111000"-(0'&D(7 downto 1));
       Y1 <="01110111"+(0'&D(7 downto 1));