Цитата(Панасенко Вадим @ Dec 8 2010, 19:55)
---Делайте все на матрице - там много портов!
---Вы где учитесь?
Мои ответы в теле Вашего сообщения
Не хотелось позорить собой свое учебное учереждение, но это Самарский аэрокосмический университет))))))))
Цитата
Реализовать это можно с помощью счетчика, подавая на него 2048кГц.
Так как счетчиков надо 30, то лучше на плис их реализовать.
---Все правильно, счетчики и дешифраторы. Передатчик получается простой, главное сделать приемник синхронизирующийся по FAS NFAS
Если буду реализовывать на ПЛИС, то могут возникнуть проблемы с разделом метрология..
Цитата
--Зачем Вам это! Кодек пропускает прозрачно спектр 300-3400 от телефона с DTMF до АТС, не надо ничего кодировать и декодировать!
---Пусть АТС сама разбирается с DTMF набором. Ваша задача передать импульсный набор! Это делается битом А в 16 канальном интервале спериодом повторения 2 мс, поскольку импульс набор 40/60мс, то 2 мс это очень маленькая погрешность.
Да точно, теперь не надо заморачиватся.
Цитата
----Зачем Вам это, делайте все на матрице ALTERA
----или разбирайтесь с готовыми фреймерами. Вот им уже нужен процессор для программирования режимов, обычно по SPI.
А для готового фреймера тоже ведь надо на кодеки подавать строб импульс. А значит по-любому нужна ПЛИС.
На какой вывод подавать сторб?
http://i066.radikal.ru/1012/d1/7585da9e1f87.pngЦитата
FSRReceive Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLKR. Following a rising FSR edge, a serial PCM word at
DR is clocked by BCLKR into the receive data register.
FSR
also initiates a decode on the previous PCM word. In the absence
of FSX, the length of the FSR pulse is used to determine
whether the I/O conforms to the Short Frame Sync or
Long Frame Sync convention.
DR
Receive Digital Data Input
BCLKR/CLKSEL
Receive Data Clock and Master Clock Frequency
Selector
If this input is a clock, it must be between 128 kHz and
4.096 MHz, and synchronous with FSR. In synchronous
applications this pin may be held at a constant level; then
BCLKX is used as the data clock for both the transmit and
receive sides, and this pin selects the assumed frequency of
the master clock (see Table 1 in Functional Description).
MCLKR/PDN
Receive Master Clock and Power–Down Control
Because of the shared DAC architecture used on these
devices, only one master clock is needed. Whenever FSX is
clocking, MCLKX is used to derive all internal clocks, and the
MCLKR/PDN pin merely serves as a power–down control. If
MCLKR/PDN pin is held low or is clocked (and at least one
of the frame syncs is present), the part is powered up. If this
pin is held high, the part is powered down. If FSX is absent
but FSR is still clocking, the device goes into receive half–
channel mode, and MCLKR (if clocking) generates the
internal clocks.
MCLKX
Transmit Master Clock
This clock is used to derive the internal sequencing clocks;
it must be 1.536 MHz, 1.544 MHz, or 2.048 MHz.
BCLKX
Transmit Data Clock
BCLKX may be any frequency between 128 kHz and
4.096 MHz, but it should be synchronous with MCLKX.
DX
Transmit Digital Data Output
This output is controlled by FSX and BCLKX to output the
PCM data word; otherwise this pin is in a high–impedance
state.
FSX
Transmit Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLKX. A rising FSX edge initiates the transmission of a
serial PCM word, clocked by BCLKX, out of DX. If the FSX
pulse is high for more than eight BCLKX periods, the DX and
TSX outputs will remain in a low–impedance state until FSX
is brought low. The length of the FSX pulse is used to determine
whether the transmit and receive digital I/O conforms to
the Short Frame Sync or to the Long Frame Sync convention.
TSX
Transmit Time Slot Indicator
This is an open–drain output that goes low whenever the
DX output is in a low–impedance state (i.e., during the transmit
time slot when the PCM word is being output) for enabling
a PCM bus driver.
ANLB
Analog Loopback Control Input (MC145564/67 Only)
When held high, this pin causes the input of the transmit
RC active filter to be disconnected from GSX and connected
to VPO+ for analog loopback testing. This pin is held low in
normal operation.
ANALOG
GSX
Gain–Setting Transmit
This output of the transmit gain–adjust operational amplifier
is internally connected to the encoder section of the
device. It must be used in conjunction with VFXI– and VFXI+
to set the transmit gain for a maximum signal amplitude of
2.5 V peak. This output can drive a 600 W load to 2.5 V peak.
VFXI–
Voice–Frequency Transmit Input (Inverting)
This is the inverting input of the transmit gain–adjust
operational amplifier.
VFXI+
Voice–Frequency Transmit Input
(Non–Inverting)
This is the non–inverting input of the transmit gain–adjust
operational amplifier.
VFRO
Voice–Frequency Receive Output
This receive analog output is capable of driving a 600 W
load to 2.5 V peak.
VPI
Voltage Power Input (MC145564/67 Only)
This is the inverting input to the first receive power amplifier.
Both of the receive power amplifiers can be powered
down by connecting this input to VBB.
VPO–
Voltage Power Output (Inverted) (MC145564/67 Only)
This inverted output of the receive push–pull power amplifiers
can drive 300 W to 3.3 V peak.
VPO+
Voltage Power Output (Non–Inverted)
(MC145554/67 Only)
This non–inverted output of the receive push–pull power
amplifier pair can drive 300 W to 3.3 V peak.
POWER SUPPLY
GNDA
Analog Ground
This terminal is the reference level for all signals, both analog
and digital. It is 0 V.
VCC
Positive Power Supply
VCC is typically 5 V.
VBB
Negative Power Supply
VBB is typically – 5
Я так понял что за это отвечают
FSXTransmit Frame Sync
This is an 8 kHz enable that must be synchronous with
Подаем 8кГц
BCLKX. A rising FSX edge initiates the transmission of a
serial PCM word, clocked by BCLKX, out of DX. If the FSX
pulse is high for more than eight BCLKX periods, the DX and
TSX outputs will remain in a low–impedance state until FSX
is brought low. The length of the FSX pulse is used to determine
whether the transmit and receive digital I/O conforms to
the Short Frame Sync or to the Long Frame Sync convention.
Подаем строб
Цитата
Это делается битом А в 16 канальном интервале спериодом повторения 2 мс, поскольку импульс набор 40/60мс, то 2 мс это очень маленькая погрешность.
Недопонял.
в ки16 хотел передавать инфу трубка снята и тд
но это все фигня, как сделать . ки 16 это 3,9мкс.
aaaa bbbb
cccc dddd
Где это кстати, нормируется как передавать сигнализацию?
Altera - делаем там фреймер Е1
.