-- ADDMACC_MACRO : In order to incorporate this function into the design,
--     VHDL      : the following instance declaration needs to be placed
--   instance    : in the architecture body of the design code.  The
--  declaration  : (ADDMACC_MACRO_inst) and/or the port declarations
--     code      : after the "=>" assignment maybe changed to properly
--               : reference and connect this function to the design.
--               : All inputs and outputs must be connected.

--    Library    : In addition to adding the instance declaration, a use
--  declaration  : statement for the UNISIM.vcomponents library needs to be
--      for      : added before the entity declaration.  This library
--    Xilinx     : contains the component declarations for all Xilinx
--   primitives  : primitives and points to the models that will be used
--               : for simulation.

--  Copy the following four statements and paste them before the
--  Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

Library UNIMACRO;
use UNIMACRO.vcomponents.all;
--  <-----Cut code below this line and paste into the architecture body---->

   -- ADDMACC_MACRO: Add and Multiple Accumulate Function implemented in a DSP48E
   --                Virtex-6
   -- Xilinx HDL Language Template, version 13.1

   ADDMACC_MACRO_inst : ADDMACC_MACRO
   generic map (
      DEVICE => "VIRTEX6",  -- Target Device: "VIRTEX6", "SPARTAN6"
      LATENCY => 4,         -- Desired clock cycle latency, 1-4
      WIDTH_PREADD => 25,   -- Pre-Adder input bus width, 1-25
      WIDTH_MULTIPLIER => 18, -- Multiplier input bus width, 1-18    
      WIDTH_PRODUCT => 48)    -- MACC output width, 1-48
   port map (
      PRODUCT => PRODUCT,     -- MACC result output, width defined by WIDTH_PRODUCT generic
      MULTIPLIER => MULTIPLIER, -- Multiplier data input, width determined by WIDTH_MULTIPLIER generic
      PREADDER1 => PREADDER1,   -- Preadder data input, width determined by WIDTH_PREADDER generic
      PREADDER2 => PREADDER2,   -- Preadder data input, width determined by WIDTH_PREADDER generic
      CARRYIN => CARRYIN, -- 1-bit carry-in input
      CE => CE,      -- 1-bit input clock enable
      CLK => CLK,    -- 1-bit clock input
      LOAD => LOAD, -- 1-bit accumulator load input
      LOAD_DATA => LOAD_DATA, -- Accumulator load data input, width defined by WIDTH_PRODUCT generic
      RST => RST    -- 1-bit input active high synchronous reset
   );
   -- End of ADDMACC_MACRO_inst instantiation

----- CELL ADDMACC_MACRO -----

library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

library UNISIM;
use UNISIM.vcomponents.all;

library STD;
use STD.TEXTIO.ALL;


entity ADDMACC_MACRO is
  generic (
            DEVICE : string := "VIRTEX6";
            LATENCY : integer := 4;
            WIDTH_PREADD : integer := 25;
            WIDTH_MULTIPLIER : integer := 18;
            WIDTH_PRODUCT : integer := 48
       );

  port (
      PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0);
      CARRYIN : in std_logic;
      CE : in std_logic;
      CLK : in std_logic;
      MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0);
      LOAD : in std_logic;
      LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0);
      PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
      PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
      RST : in std_logic
     );
end entity ADDMACC_MACRO;

Generating Report ...


Fatal Error.Occurred at file XXX.twx, line 340, column 320811. An exception occurred! Type:UTFDataFormatException, Message:invalid bytes Г , [ of 3-byte sequence.
Number of warnings: 0
Total time: 6 secs

Process "Generate Post-Place & Route Static Timing" completed successfully

genvar i;
generate  
for (i=0; i < 31; i=i+1)  
begin: lbl
    sync s( .in_async(err_in[i]),.out_sync(err_in_synced[i]),.clk(clk));
    always @(posedge clk or posedge reset)
        if (reset) err[i]<=1'b0;
        else if (err_in_synced[i]==1'b1)err[i]<=1'b1;
        
assign ERR_IRQ = ~(ERR_IRQ|err[i]);
end  
endgenerate

Regenerate Core - cmos_mem: All required files are available.

Process "Regenerate Core" completed successfully
Regenerate Core - FIFO_CMOS: All required files are available.

Process "Regenerate Core" completed successfully
Regenerate Core - CLK_GEN: All required files are available.

Process "Regenerate Core" completed successfully
Regenerate Core - ddr2ctl: All required files are available.

Process "Regenerate Core" failed
Regenerate Core - ICON_bud_cs4_cs5: All required files are available.

Process "Regenerate Core" completed successfully
Regenerate Core - ILA_bud_cs4_cs5: All required files are available.

Process "Regenerate Core" completed successfully

Process "Regenerate Core" failed
Regenerate Core - ICON_bud_cs4_cs5: All required files are available.