#define MCFG_CLK_DIV20      0x00000038  /* MDC = hclk / 20  */

// configure port-pins for use with LAN-controller,
// reset it and send the configuration-sequence
//mode = 0 - slow mode, 1 - fast
int Init_EMAC(int mode)
{
// Keil: function modified to access the EMAC
// Initializes the EMAC ethernet controller
  unsigned int regv,regv1,tout,id1,id2, moduleid, model=0, twait;

  twait = 0x100000;
  if(mode)  twait = 0x10000;

   /* Power Up the EMAC controller. */
   LPC_SC->PCONP |= 0x40000000;
  /* Enable P1 Ethernet Pins. */
    LPC_PINCON->PINSEL2 = 0x50150105;

#ifdef __LPC175x
  /* LPC175x devices, use software MII management. */  
  LPC_PINCON->PINSEL4 &= ~0x000F0000;
  LPC_GPIO2->FIODIR |= MDC;
#else
  /* LPC176x devices, no MDIO, MDC remap. */
  LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
#endif
  /* Reset all EMAC internal modules. */
  LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
  LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
  
  /* A short delay after reset. */
  for (tout = 100; tout; tout--);

  /* Initialize MAC control registers. */
  LPC_EMAC->MAC1 = MAC1_PASS_ALL;
  LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;

  LPC_EMAC->MAXF = ETH_MAX_FLEN;
  LPC_EMAC->CLRT = CLRT_DEF;
  LPC_EMAC->IPGR = IPGR_DEF;


/*PCLK=18MHz, clock select=6, MDC=18/6=3MHz */  
   /* Enable Reduced MII interface. */
   LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
   for (tout = 100; tout; tout--);
   LPC_EMAC->MCFG = MCFG_CLK_DIV20;

  regv = read_PHY (PHY_REG_BMSR);
  regv1= read_PHY (PHY_REG_STS);


  /* Enable Reduced MII interface. */
  LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;


  /* Put the DP83848C in reset mode */
  write_PHY (PHY_REG_BMCR, 0x8000);

  /* Wait for hardware reset to end. */
  for (tout = 0; tout < 0x100000; tout++) {
    regv = read_PHY (PHY_REG_BMCR);
    if (!(regv & 0x8000)) {
      /* Reset complete */
      break;
    }
  }

  /* Check if this is a DP83848C PHY. */
  id1 = read_PHY (PHY_REG_IDR1);
  id2 = read_PHY (PHY_REG_IDR2);

  moduleid = ((id1 << 16) | (id2 & 0xFFF0));
  if ( moduleid == DP83848C_ID ) model=1;
  else if (  moduleid == KS8721B_ID ) model=2;

/* Use autonegotiation about the link speed. */
    write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);

    /* Wait to complete Auto_Negotiation. 0x10000*/
    for (tout = 0; tout < twait; tout++) {
      regv = read_PHY (PHY_REG_BMSR);
      if (regv & 0x0020) {
        /* Autonegotiation Complete. */
        break;
      }
      if (tout > 0x100 && (LPC_EMAC->MIND & MIND_NOT_VAL))
          break;
    }

    if (regv & 0x0020)
    {
      /* Autonegotiation Complete. */
    } else {
        return 1; /* Ωαßσδⁿ φσ ∩εΣΩδ■≈σφ */
    }


  /* Check the link status. */
  for (tout = 0; tout < 0x10000; tout++)
  {
//    regv = read_PHY (PHY_REG_STS);
//    if (regv & 0x0001) {
//      /* Link is on. */
//      break;
//    }
    regv = read_PHY (PHY_REG_BMSR);
    if (regv & 0x0004) {
      /* Link is on. */
      break;
    }

  }

/*****************/
if(model == 2)
{ regv = read_PHY (PHY_REG_STS2);
   regv=(regv>>2)&7;
  if ((regv==5)||(regv==6))
  {/* Full duplex is enabled. */
    LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
    LPC_EMAC->Command |= CR_FULL_DUP;
    LPC_EMAC->IPGT     = IPGT_FULL_DUP;
  }
  else {
    /* Half duplex mode. */
    LPC_EMAC->IPGT = IPGT_HALF_DUP;
  }

  /* Configure 100MBit/10MBit mode. */
   if ((regv==1)||(regv==5))
  {/* 10MBit mode. */
    LPC_EMAC->SUPP = 0;
  } else {
    /* 100MBit mode. */
    LPC_EMAC->SUPP = SUPP_SPEED;
  }
/*****************/
} else {
     regv = read_PHY (PHY_REG_STS);

  /* Configure Full/Half Duplex mode. */
  if (regv & 0x0004) {
    /* Full duplex is enabled. */
    LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
    LPC_EMAC->Command |= CR_FULL_DUP;
    LPC_EMAC->IPGT     = IPGT_FULL_DUP;
  }
  else {
    /* Half duplex mode. */
    LPC_EMAC->IPGT = IPGT_HALF_DUP;
  }

  /* Configure 100MBit/10MBit mode. */
  if (regv & 0x0002) {
    /* 10MBit mode. */
    LPC_EMAC->SUPP = 0;
  }
  else {
    /* 100MBit mode. */
    LPC_EMAC->SUPP = SUPP_SPEED;
  }
} /*****************/

  /* Set the Ethernet MAC Address registers */
  LPC_EMAC->SA0 = (MYMAC_1 << 8) | MYMAC_2;
  LPC_EMAC->SA1 = (MYMAC_3 << 8) | MYMAC_4;
  LPC_EMAC->SA2 = (MYMAC_5 << 8) | MYMAC_6;

  /* Initialize Tx and Rx DMA Descriptors */
  rx_descr_init ();
  tx_descr_init ();

  /* Receive Broadcast and Perfect Match Packets */
  LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;                    

  /* Enable EMAC interrupts. */
  LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;

  /* Reset all interrupts */
  LPC_EMAC->IntClear  = 0xFFFF;

  /* Enable receive and transmit mode of MAC Ethernet core */
  LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
  LPC_EMAC->MAC1     |= MAC1_REC_EN;

  return 0;
}