library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity antitwit_fix is
Port ( INSIG : in STD_LOGIC;
N1kHz : in STD_LOGIC;
OUTSIG : out STD_LOGIC);
end antitwit_fix;

architecture Behavioral of antitwit_fix is

signal INT1, INT2,: STD_LOGIC; -- декларируем внутренние сигналы
signal BUS1: STD_LOGIC_VECTOR (7 downto 0):= ”00000000”;


begin

process (N1kHz)
begin
if N1kHz 'event and N1kHz = ‘1’ then
if INT1 = '1’ then
BUS1 <= BUS1 + 1;
end if;
end if;
end process;

INT1 <= ‘1’ when  or INSIG = ‘1’ else ‘0’;
OUTSIG <= INT2;
INT2 <= ‘0’ when BUS1 = ”00000000” else ‘1’;
end Behavioral;

always@(posedge clk)
  counter <= counter + 1'b1;

module async
(
  clk25MHz,

  nrst1KHz,
  nrst25MHz,

  cntr1KHz
);
input        clk25MHz;

input        nrst1KHz;
input        nrst25MHz;

output [7:0] cntr1KHz;

reg          clk1KHz;
reg   [13:0] cntr25MHz;

wire         comp = ((12500-1) == cntr25MHz);

always @(posedge clk25MHz or negedge nrst25MHz)
begin
  if (nrst25MHz == 0)
  begin
    clk1KHz <= 0;
    cntr25MHz <= 0;
  end
  else
  begin
    if (comp)
    begin
      clk1KHz <= !clk1KHz;
      cntr25MHz <= 0;
    end
    else
    begin
      cntr25MHz <= cntr25MHz + 1;
    end
  end
end

reg [7:0] cntr1KHz;

always @(posedge clk1KHz or negedge nrst1KHz)
begin
  if (nrst1KHz == 0)
  begin
    cntr1KHz <= 0;
  end
  else
  begin
    cntr1KHz <= cntr1KHz + 1;
  end
end

endmodule

# Clock constraints
create_clock -name clk25MHz -period 40.000 [get_ports {clk25MHz}] -waveform {0.000 20.000}

# tsu/th constraints
set_input_delay -clock clk25MHz -min 1.0 [get_ports nrst25MHz]
set_input_delay -clock clk25MHz -max 2.0 [get_ports nrst25MHz]

create_generated_clock -name clk1KHz -source [get_ports clk25MHz] -divide_by 25000 [get_pins clk1KHz_reg/Q]

set_clock_groups -asynchronous -group clk25MHz -group clk1KHz

set_input_delay -clock clk1KHz -min 1.0 [get_ports nrst1KHz]
set_input_delay -clock clk1KHz -max 2.0 [get_ports nrst1KHz]

# Constrain the output I/O path
set_output_delay -clock clk1KHz -min 0.000 [all_outputs]
set_output_delay -clock clk1KHz -max 1.000 [all_outputs]

module async
(
  clk25MHz,
  clk1KHz
);
input clk25MHz;
output reg clk1KHz;

reg   [13:0] cntr25MHz;

always @(posedge clk25MHz)
    begin
    if (cntr25MHz == 12499)
        begin
        clk1KHz <= !clk1KHz;
        cntr25MHz <= 0;
        end
    else
        begin
        cntr25MHz <= cntr25MHz + 1;
        end
    end
endmodule