Цитата(alexadmin @ Oct 14 2015, 12:26)
А если самим ISE синтезировать, не пробовали?
ISE не дружит с systemverilog, надо много чего переписывать.
... больше света в темную комнату
Код
Mapping to part: xc6slx9tqg144-2
Cell usage:
DCM_SP 1 use
FD 94 uses
FDE 2720 uses
FDR 245 uses
FDRE 3189 uses
FDSE 4 uses
GND 33 uses
MUXCY 12 uses
MUXCY_L 233 uses
MUXF7 290 uses
MUXF8 144 uses
VCC 33 uses
XORCY 209 uses
fifo_w4d16_spartan6 1 use
LUT1 109 uses
LUT2 202 uses
LUT3 934 uses
LUT4 991 uses
LUT5 527 uses
LUT6 1570 uses
LUT6_2 5 uses
I/O ports: 57
I/O primitives: 53
IBUF 12 uses
IBUFG 1 use
OBUF 40 uses
BUFG 2 uses
SRL primitives:
SRLC32E 48 uses
I/O Register bits: 0
Register bits not including I/Os: 6252 (50%)
Global Clock Buffers: 2 of 16 (12%)
Total load per clock:
clk8x|CLKFX_BUF_derived_clock: 6301
clk8x|CLK0_BUF_derived_clock: 1
clock_p51: 1
Mapping Summary:
Total LUTs: 3773 (61%)
Distribution of All Consumed LUTs = SRL + LUT1 + LUT2 + LUT3 + LUT4 + LUT5 + LUT6 + LUT6_2- HLUTNM/2
Distribution of All Consumed Luts 3773 = 48 + 109 + 202 + 934 + 991 + 527 + 1570 + 5- 1226/2
Number of unique control sets: 130
Region Summary:
Other LUTs: 4338 Other Registers: 6252
Mapper successful!
Xilinx пишет
Код
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 6,282 out of 11,440 54%
Number used as Flip Flops: 6,282
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 3,779 out of 5,720 66%
Number used as logic: 3,717 out of 5,720 64%
Number using O6 output only: 2,880
Number using O5 output only: 70
Number using O5 and O6: 767
Number used as ROM: 0
Number used as Memory: 48 out of 1,440 3%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 48
Number using O6 output only: 48
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 14
Number with same-slice register load: 0
Number with same-slice carry load: 14
Number with other load: 0
Slice Logic Distribution:
Number of MUXCYs used: 320 out of 2,860 11%
Number of LUT Flip Flop pairs used: 8,885
Number with an unused Flip Flop: 2,732 out of 8,885 30%
Number with an unused LUT: 5,106 out of 8,885 57%
Number of fully used LUT-FF pairs: 1,047 out of 8,885 11%
Number of unique control sets: 180
Number of slice register sites lost
to control set restrictions: 742 out of 11,440 6%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 53 out of 102 51%
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 32 0%
Number of RAMB8BWERs: 1 out of 64 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 2 out of 16 12%
Number used as BUFGs: 2
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 4 25%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 0 out of 16 0%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Цитата(Vascom @ Oct 14 2015, 11:52)
До окончания роутинга все оценки таймингов и занятых ресурсов - приблизительные.
огорчает приближение +- полчипа
