//  AGC
    reg [23:0] agc_control = 24'd0; // 83888608
   wire [23:0] max_gain = 23'd8000000 - step_up;
    wire [23:0] min_gain = 23'd1 + step_dwn;
    wire [23:0] step_up = 23'd56000; // 1 sec
    wire [23:0] step_dwn = 16'd560;  // 10 msec
    wire [23:0] gate = 24'd8000000;
    
    
    wire signed [47:0] mult_out;
   mult_24Sx24S_w agc_mult(det_out, agc_control, mult_out);
    wire signed [23:0] agc_mult_out = mult_out[35:12];
        

   reg [5:0] state = 0;
    wire [23:0] mod = agc_mult_out[23] ? ~agc_mult_out : agc_mult_out;
   always @(posedge clock)
    begin
       case (state)
        0: if(det_out_strobe) state <= state + 1'd1;
        1,2,3 : state <= state + 1'd1;
        4: begin
              if(mod > gate) if(agc_control > min_gain) agc_control <= agc_control - step_dwn;
             if(mod < gate) if(agc_control < max_gain) agc_control <= agc_control + step_up;  
                state <= state + 1'd1;
            end
       5,6,7: state <= state + 1'd1;
       8: begin agc_out <= agc_mult_out; agc_out_strobe <= 1; state <= state + 1'd1; end
       9: begin agc_out_strobe <= 0; state <= 1'd0; end    
        default: state <= 1'd0;
        endcase
      

    end