function int number_of_bits_for_value_representation(input int value);
  int temp;
  temp    =    2;
  number_of_bits_for_value_representation    =    1;
  while (temp<=value)
    begin
      number_of_bits_for_value_representation = number_of_bits_for_value_representation+1;
      temp  = temp*2;
    end
endfunction

library ieee;
library ieee;
use IEEE.std_logic_1164.all,
IEEE.std_logic_unsigned.all,
IEEE.std_logic_arith.all;

entity dc_fifo is
GENERIC
(
WIDTHA : integer := 8;
WIDTH : integer := 8
);
PORT
(
rst : in std_logic;

wr_clk: in std_logic; -- write clock
wr_ena: in std_logic; -- write clock enable
wr_dta: in std_logic_vector(WIDTH-1 downto 0); -- write data

rd_clk: in std_logic; -- read clock
rd_ena: in std_logic; -- read enable
rd_dta: out std_logic_vector(WIDTH-1 downto 0); -- read data

rd_empty, rd_full, rd_half : out boolean; -- read side status
wr_empty, wr_full, wr_half : out boolean -- write side status
);

end dc_fifo;


architecture behavior of dc_fifo is

constant N : integer := (2**WIDTHA);
constant ADR_MAX : integer := (2**WIDTHA)-1;

subtype ADDRESS is integer range 0 to ADR_MAX;
subtype DATA is std_logic_vector(WIDTH-1 downto 0);
type FIFO_RAM is array (0 to ADR_MAX) of DATA;

-- binary representation of addersses
signal wr_b_adr : ADDRESS;
signal rd_b_adr : ADDRESS;
-- gray code representation of addresses
signal wr_g_adr : ADDRESS;
signal rd_g_adr : ADDRESS;
-- next write signal
signal wr_add : integer range 0 to 1;
signal wr_next : ADDRESS;

signal ram : FIFO_RAM;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ram : signal is "no_rw_check";


function bin2gray( a : ADDRESS ) return ADDRESS is
variable u, v : std_logic_vector( WIDTHA-1 downto 0 );
variable b : ADDRESS;
begin
v := conv_std_logic_vector( a, WIDTHA );
u := v xor ('0' & v(WIDTHA-1 downto 1));
b := ADDRESS(conv_integer('0' & u));
return b;
end;


function gray2bin( a : ADDRESS ) return ADDRESS is
variable u, v : std_logic_vector( WIDTHA-1 downto 0 );
variable b : ADDRESS;
variable x : std_logic;
begin
v := conv_std_logic_vector( a, WIDTHA );

for i in u'range loop
x := '0';
for j in v'range loop
if (j>=i) then
x := x xor v(j);
end if;
end loop;
u(i) := x;
end loop;

b := ADDRESS(conv_integer('0' & u));
return b;
end;

function fifo_size( w, r : ADDRESS ) return ADDRESS is
constant N : integer := (2**WIDTHA);
variable b : ADDRESS;
begin
b := (N + w - r) mod N;
return b;
end;


begin

wr_add <= 1 when wr_ena='1' else 0;
wr_next <= ( wr_b_adr + wr_add ) mod N;

WRITE_PART:process(rst,wr_clk)
begin

if rst='0' then
wr_b_adr <= 0;
wr_g_adr <= bin2gray( 0 );
wr_empty <= true;
wr_full <= false;
wr_half <= false;
elsif rising_edge(wr_clk) then

-- fix values. Needed for better inferring RAM block
wr_b_adr <= wr_next;
wr_g_adr <= bin2gray( wr_next );

wr_empty <= fifo_size( wr_b_adr, gray2bin(rd_g_adr) ) < 2;
wr_full <= fifo_size( wr_b_adr, gray2bin(rd_g_adr) ) >= N-4;
wr_half <= fifo_size( wr_b_adr, gray2bin(rd_g_adr) ) >= N/2;

end if;
end process;

RAM_STORE:process(wr_clk)
begin
-- perform write, no reset dependency
if rising_edge(wr_clk) then
if wr_ena='1' then
ram(wr_b_adr) <= wr_dta;
end if;
end if;
end process;


READ_PART:process(rst,rd_clk)
begin

if rst='0' then
rd_b_adr <= 0;
rd_g_adr <= bin2gray( 0 );
rd_empty <= true;
rd_full <= false;
rd_half <= false;
elsif rising_edge(rd_clk) then
if rd_ena='1' then
rd_b_adr <= (rd_b_adr+1) mod N;
rd_g_adr <= bin2gray( (rd_b_adr+1) mod N );
end if;
-- fifo status on the reader part
rd_empty <= fifo_size( gray2bin(wr_g_adr), rd_b_adr ) <= conv_integer(rd_ena);
rd_full <= fifo_size( gray2bin(wr_g_adr), rd_b_adr ) >= N-2;
rd_half <= fifo_size( gray2bin(wr_g_adr), rd_b_adr ) >= N/2;
end if;
end process;

RAM_PEEK:process(rd_clk)
begin
-- read register for dual-port RAM inferring
if rising_edge(rd_clk) then
if rd_ena='1' then
rd_dta <= ram(rd_b_adr);
end if;
end if;
end process;


end behavior;

fifo_size( gray2bin(wr_g_adr), rd_b_adr ) <= conv_integer(rd_ena)

wr_b_adr <= gray2bin(wr_g_adr);
rd_empty <= fifo_size( wr_b_adr, rd_b_adr ) <= conv_integer(rd_ena)

DFFE ff0 (.d(Din[0]), .ena(ena), .clk(clk_GN), .q(iDin[0]));
DFFE ff1 (.d(Din[1]), .ena(ena), .clk(clk_GN), .q(iDin[1]));
DFFE ff2 (.d(Din[2]), .ena(ena), .clk(clk_GN), .q(iDin[2]));
DFFE ff3 (.d(Din[3]), .ena(ena), .clk(clk_GN), .q(iDin[3]));

ff[3..0]: dffe;
ff.(d, ena, clk, q) = (Din[3..0], ena, clk_GN, iDin[3..0]);

DFFE ff_all[3:0] (.d(Din), .ena(ena), .clk(clk_GN), .q(iDin));

always_ff@(posedge adc_mclk_mux or negedge rst_i) begin 27,648 MHz
    if (!rst_i) counter<='0;
    else if (!TRIG3_stb && TRIG3_rg_n)   counter<=32'd0; //start condition
    else counter<=counter+1'b1;
end

always_ff@(negedge adc_mclk_mux or negedge rst_i) begin
    if (!rst_i) cnt_rg_HADC<='0;
        else if (!ff_hold) cnt_rg_HADC<=counter;
end

always_ff@(posedge clk_i or negedge rst_i) begin
    if (!rst_i) fHold_value<='0;
        else if (!IOMS && !LRD) begin
                  if         (LA==pIOMS_ADC_CTRL_CNTR_L)    fHold_value<='0; //LSB      
                  else if    (LA==pIOMS_PXI_MUX_CNTR_H)      fHold_value<='1; //MSB        
        end                                         
end


always_ff@(negedge adc_mclk_mux or negedge rst_i) begin//posedge
if (!rst_i)  ff_hold<='0;
else if ( fHold_value && IOMS)  ff_hold<='1;
else if (!fHold_value && IOMS)  ff_hold<='0;

end

reg [3:0] dffe_rg = 4'h0;

always @(posedge clk_GN)
begin
if (ena)        dffe_rg  <= Din
end

module lc(input in, output out);
  LCELL l (.in(in), .out(out));
endmodule

wire [7:0] p, q;
lc lcq[7:0] (p, q);

always_ff @ (posedge clk)
    if (ena) iDin <= Din;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity FIFO is
generic (Addr_Size : natural := 3; -- Разрядность адреса (глубина FIFO)
Data_Size : natural := 32); -- Разрядность данных
port (RST : in std_logic; -- Сброс
CLK_WR : in std_logic; -- Тактовый сигнал для записи
WE : in std_logic; -- Разрешение записи (Write Enable)
Data_WR : in std_logic_vector(Data_Size - 1 downto 0); -- Данные, записываемые в буфер
CLK_RD : in std_logic; -- Тактовый сигнал для чтения
RE : in std_logic; -- Разрешение чтения (Read Enable)
Data_RD : out std_logic_vector(Data_Size - 1 downto 0); -- Данные, читаемые из буфера
Full : out std_logic; -- Флаг того, что буфер полон
Empty : out std_logic); -- Флаг того, что буфер пуст
end entity FIFO;


architecture RTL of FIFO is

type FIFO_RAM_Type is array (0 to 2**Addr_Size - 1) of std_logic_vector(Data_Size - 1 downto 0);
signal FIFO_RAM : FIFO_RAM_Type;

--================================================================================
================================================--
-- Функция преобразования из двоичного кода в код Грея: --
--================================================================================
================================================--
function Bin_to_Gray (D: unsigned) return unsigned is
variable Q : unsigned(D'range);
begin
Q := ('0' & D(D'high downto 1)) xor D;
return Q;
end function Bin_to_Gray;
--================================================================================
================================================--


--================================================================================
================================================--
-- Функция преобразования кода Грея в двоичный код: --
--================================================================================
================================================--
function Gray_to_Bin (D: in unsigned) return unsigned is
variable Q: unsigned(D'high downto D'low);
begin
Q(D'high) := D(D'high);
for i in D'high - 1 downto D'low loop
Q(i) := D(i) xor Q(i + 1);
end loop;
return Q;
end function;
--================================================================================
================================================--

signal Addr_Write_Gray : unsigned(Addr_Size downto 0); -- Адрес записи данных в буфер в коде Грея
signal Addr_Write_Gray_Next : unsigned(Addr_Size downto 0); -- Следующий адрес записи данных в буфер в коде Грея
signal Addr_Read_Gray : unsigned(Addr_Size downto 0); -- Адрес чтения данных из буфера в коде Грея

signal Addr_Write_Bin : unsigned(Addr_Size downto 0); -- Адрес записи данных в буфер в двоичном коде
signal Addr_Write_Bin_Next : unsigned(Addr_Size downto 0); -- Следующий адрес записи данных в буфер в двоичном коде
signal Addr_Read_Bin : unsigned(Addr_Size downto 0); -- Адрес чтения данных из буфера в двоичном коде

signal WE_Allow : std_logic; -- Разрешение записи данных в FIFO-буфер
signal RE_Allow : std_logic; -- Разрешение чтения данных из FIFO-буфера

signal Full_Match : std_logic; -- Сравнение адресов записи и чтения для флага того, что буфер полон
signal Empty_Match : std_logic; -- Сравнение адресов записи и чтения для флага того, что буфер пуст
begin

-- Адрес записи данных в буфер в двоичном коде: --
process(RST, CLK_WR)
begin
if (RST = '1') then
Addr_Write_Bin <= (others => '0');
elsif (Rising_Edge(CLK_WR)) then
if(WE_Allow = '1') then
Addr_Write_Bin <= Addr_Write_Bin + 1;
end if;
end if;
end process;

-- Следующий адрес записи данных в буфер в двоичном коде: --
process(RST, CLK_WR)
begin
if (RST = '1') then
Addr_Write_Bin_Next <= TO_UNSIGNED(1, Addr_Size + 1);
elsif (Rising_Edge(CLK_WR)) then
if(WE_Allow = '1') then
Addr_Write_Bin_Next <= Addr_Write_Bin_Next + 1;
end if;
end if;
end process;

-- Адрес записи данных в FIFO-буфер в коде Грея: --
Addr_Write_Gray <= Bin_to_Gray(Addr_Write_Bin);

-- Следующий адрес записи данных в буфер в коде Грея: --
Addr_Write_Gray_Next <= Bin_to_Gray(Addr_Write_Bin_Next);

-- Адрес чтения данных из буфера в двоичном коде: --
process(RST, CLK_RD)
begin
if (RST = '1') then
Addr_Read_Bin <= (others => '0');
elsif (Rising_Edge(CLK_RD)) then
if(RE_Allow = '1') then
Addr_Read_Bin <= Addr_Read_Bin + 1;
end if;
end if;
end process;

-- Адрес чтения данных из FIFO-буфера: --
Addr_Read_Gray <= Bin_to_Gray(Addr_Read_Bin);

-- Запись данных в FIFO-буфер: --
process
begin
wait until (rising_edge(CLK_WR));
if(WE_Allow = '1') then
FIFO_RAM(TO_INTEGER(Addr_Write_Gray(Addr_Size - 1 downto 0))) <= Data_WR;
end if;
end process;

-- Чтение данных из FIFO-буфера: --
process
begin
wait until (rising_edge(CLK_RD));
if(RE_Allow = '1') then
Data_RD <= FIFO_RAM(TO_INTEGER(Addr_Read_Gray(Addr_Size - 1 downto 0)));
end if;
end process;

-- Разрешение записи данных в FIFO-буфер: --
WE_Allow <= '1' when (WE = '1' and Full_Match = '0') else '0';

-- Разрешение чтения данных из FIFO-буфера: --
RE_Allow <= '1' when (RE = '1' and Empty_Match = '0') else '0';

-- Сравнение адресов записи и чтения для флага того, что буфер полон: --
Full_Match <= '1' when (Addr_Write_Bin(Addr_Size - 1 downto 0) = Addr_Read_Bin(Addr_Size - 1 downto 0) and Addr_Write_Bin(Addr_Size) /= Addr_Read_Bin(Addr_Size) and (RE = '0' or (RE = '1' and WE = '1'))) else '0';

-- Флаг того, что буфер полон: --
Full <= '1' when (Full_Match = '1' or (Addr_Write_Bin_Next(Addr_Size - 1 downto 0) = Addr_Read_Bin(Addr_Size - 1 downto 0) and Addr_Write_Bin_Next(Addr_Size) /= Addr_Read_Bin(Addr_Size) and (RE = '0' and WE = '1'))) else '0';

-- Сравнение адресов записи и чтения для флага того, что буфер пуст: --
Empty_Match <= '1' when (Addr_Write_Bin = Addr_Read_Bin and (WE = '0' or (RE = '1' and WE = '1'))) else '0';

-- Флаг того, что буфер пуст: --
Empty <= Empty_Match;
end architecture RTL;

        process (add_sub_res,point_cnt,cmp_res) begin        
            for j in 15 downto 0 loop
                for i in 15 downto 0 loop
                    if ((j = i) or (i > point_cnt)) then cmp_res(j)(i) <= '1';
                    elsif (j > point_cnt) then cmp_res(j)(i) <= '0';
                    else
                        if (j > i) then cmp_res(j)(i) <= not cmp_res(i)(j);
                        else
                            if (add_sub_res(j) < add_sub_res(i)) then cmp_res(j)(i) <= '1'; else cmp_res(j)(i) <= '0'; end if;
                        end if;
                    end if;
                end loop;
            end loop;
        end process;

        cmp_res_reg <= cmp_res;    

    --    process (cmp_res_reg) begin                    -- определение: единица, если все биты cmp_res(i) == единицы
          
and_loop:        for i in 0 to 15 generate
                      cmp_res_and(i) <=    cmp_res_reg(i)(0) and cmp_res_reg(i)(1) and cmp_res_reg(i)(2) and cmp_res_reg(i)(3) and cmp_res_reg(i)(4) and cmp_res_reg(i)(5) and cmp_res_reg(i)(6) and cmp_res_reg(i)(7) and
                            cmp_res_reg(i)(8) and cmp_res_reg(i)(9) and cmp_res_reg(i)(10) and cmp_res_reg(i)(11) and cmp_res_reg(i)(12) and cmp_res_reg(i)(13) and cmp_res_reg(i)(14) and cmp_res_reg(i)(15);                    
            --end loop;
        end generate;
        

s1: with cmp_res_and select
    point_find_result <= 0 when "0000000000000001",
                1 when     "0000000000000010",
                2 when    "0000000000000100",
                3 when    "0000000000001000",
                4 when    "0000000000010000",
                5 when    "0000000000100000",
                6 when    "0000000001000000",
                7 when    "0000000010000000",
                8 when    "0000000100000000",
                9 when    "0000001000000000",
                10 when    "0000010000000000",
                11 when    "0000100000000000",
                12 when    "0001000000000000",
                13 when    "0010000000000000",
                14 when    "0100000000000000",
                15 when others;